Tackling Moore's Law goal of DARPA initiativeStory
September 06, 2018
Defense Advanced Research Projects Agency (DARPA) officials kicked off the Electronics Resurgence Initiative (ERI) summit in July 2018 by selecting teams to tackle the three technology pillars - materials/integration, architectures, and design - that will ultimately address Moore's Law. The prediction by Intel cofounder Gordon Moore in 1965 that transistors were shrinking so fast that every year twice as many could fit onto a chip was adjusted in 1975 adjusted to a doubling every two years, and is now defined as a doubling every 18 months.
Defense Advanced Research Projects Agency (DARPA) officials kicked off the Electronics Resurgence Initiative (ERI) summit in July 2018 by selecting teams to tackle the three technology pillars – materials/integration, architectures, and design – that will ultimately address Moore’s Law. The prediction by Intel cofounder Gordon Moore in 1965 that transistors were shrinking so fast that every year twice as many could fit onto a chip was adjusted in 1975 adjusted to a doubling every two years, and is now defined as a doubling every 18 months.
Dr. Bill Chappell, the director of DARPA’s Microsystems Technology Office, explains that at this point “we are at an inflection point – Moore’s inflection – which is what we termed it at DARPA.”
That inflection point comes with the “skyrocketing costs of doing business in the electronics market mixed with the foreign investment that is flowing into the marketplace,” Chappell continues. “On top of that, we have a value chain, which is pushing more and more of the value to the application and software level, away from some of the base semiconductor investments. DARPA decided, because of this confluence of events, we would have an increased concentration on the basics of electronics and the basics of semiconductors.”
The launch of the ERI summit had sessions focusing on each pillar. Under the materials/integration thrust, DARPA program managers enacted the Three Dimensional Monolithic System-on-a-Chip (3DSoC) and the Foundations Required for Novel Compute (FRANC) programs. 3DSoC members include researchers from Stanford University, MIT, and Skywater Technology Foundry. On the FRANC team: HRL Laboratories; Applied Materials; Ferric, Inc.; UCLA; University of Minnesota; and University of Illinois at Urbana-Champaign.
HRL Laboratories is working alongside team members to produce neuromorphic circuit architectures. The end result has the potential to create a “computing architecture [that is] built entirely with biomimetic memristors, using no transistors or other common types of active devices,” says Wei Yi, HRL Principal Investigator (PI).
“In this program we aim to develop efficient neuromorphic circuit architectures based on memristors instead of complementary metal-oxide semiconductor (CMOS) transistors,” co-PI Jose Cruz-Albrecht says. “Neuromorphic processors that use just CMOS devices have difficulty efficiently merging memory and computation with very compact circuitry. Most require several transistors to implement just the memory portion of a single synapse, additional transistors for the most basic synaptic computation, and still more transistors for complex synaptic computations that include adaptation mechanisms. In this program we plan to develop all-memristor circuit architectures that efficiently merge memory and computation. An electronic synapse that includes memory, computation, and adaptation could be designed with as little as one memristor, which could enable more compact and energy-efficient neuromorphic processors.”
For the architectures pillar, according to DARPA materials, teams selected for the Software Defined Hardware (SDH) program include Intel, NVIDIA, Qualcomm, STR, Georgia Institute of Technology, Stanford University, University of Michigan, University of Washington, and Princeton University. IBM, Oak Ridge National Labs, Arizona State University, and Stanford University will be working for the Domain-specific System on Chip (DSSoC) program.
The team is attempting to “build systems with self-introspection and data introspection so that both the chip can morph to be what it needs as the graph changes from a sparse problem to a dense problem, so it can analyze the data in real time and have the reconfigurability of the chip to change along with its data needs on the microsecond or millisecond timescales,” Chappell says.
Lastly, the design area research teams will focus primarily in the Intelligent Design of Electronic Assets (IDEA) program and the Posh Open Source Hardware (POSH) program. Team members include the University of California, San Diego; Northrop Grumman Mission Systems; Cadence Design Systems; Xilinx; Synopsys; University of Southern California; Princeton University; and Sandia National Laboratories, per DARPA officials.
Under DARPA’s IDEA program, NVIDIA will work with Cadence Design Systems to implement machine-learning algorithms to enable full automation. IDEA’s complementary program, POSH, will “create an ethos of sharing in the hardware community that’s similar to what the software community uses,” Chappell explains. “Ultimately what that comes down to is trusting a design that you may have had many different contributors, which will only be done if we have a pretty radical revolution in the underpinnings of verification. Even though it’s an open source hardware program, it’s all about verifying the functionality of these hardware blocks … so it’s very important that we have full knowledge of every design choice that went into an IP block.
“And one way to get there is through open source,” Chappell continues. “We don’t actually care if it’s open source or not. We want to have full knowledge of how something is going to work before it is utilized in an electronics system.”