Military Embedded Systems

DARPA SyNAPSE program develops low-power, brain-like chip


August 20, 2014

John McHale

Editorial Director

Military Embedded Systems

WASHINGTON. Researchers funded by the Defense Advanced Research Projects Agency (DARPA) have developed a computer chip with an architecture inspired by the neuronal structure of the brain that requires only a fraction of the electrical power of conventional chips. Defense applications where electrical power is limited such as mobile robots and remote sensors would benefit from the energy savings of the chip, which uses 100 times less power for complex processing than current devices.

IBM experts in San Jose, Calif., designed the chip under DARPA’s Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) program. It is loaded with more than five billion transistors and has more than 250 million “synapses,” or programmable logic points, that are analogous to the connections between neurons in the brain. While it is still orders of magnitude fewer than the number of actual synapses in the human brain, it marks a big step toward making ultra-high performance, low-power neuro-inspired systems a reality, according to the DARPA release.

Tasks such as perception and pattern recognition, audio processing, and motor control -- people and animals perform effortlessly -- are difficult for traditional computing architectures to do without consuming a great deal of power. Biological systems consume much less energy than current computers attempting the same tasks. The SyNAPSE program was formed to speed development of a brain-inspired chip that could perform difficult perception and control tasks while simultaneously achieving significant energy savings.

The SyNAPSE-developed chip, which may be tiled to create large arrays, has one million electronic neurons and 256 million electronic synapses between neurons. Built on Samsung Foundry's 28 nanometer process technology, the 5.4 billion transistor chip has one of the highest transistor counts of any chip ever produced, according to the DARPA release. Each chip consumes under 100 milliWatts of electrical power during operation. When applied to benchmark tasks of pattern recognition, the new chip showed two orders of magnitude in energy savings compared to state-of-the-art traditional computing systems.

The high energy efficiency is accomplished, in part, by distributing data and computation across the chip, alleviating the need to move data over large distances. The chip also runs in an asynchronous manner, processing and transmitting data only as required, similar to how a brain functions.

"Computer chip design is driven by a desire to achieve the highest performance at the lowest cost," says Gill Pratt, DARPA program manager. "Historically, the most important cost was that of the computer chip. But Moore’s law—the exponentially decreasing cost of constructing high-transistor-count chips—now allows computer architects to borrow an idea from nature, where energy is a more important cost than complexity, and focus on designs that gain power efficiency by sparsely employing a very large number of components to minimize the movement of data. IBM’s chip, which is by far the largest one yet made that exploits these ideas, could give unmanned aircraft or robotic ground systems with limited power budgets a more refined perception of the environment, distinguishing threats more accurately and reducing the burden on system operators. Our troops often are in austere environments and must carry heavy batteries to power mobile devices, sensors, radios and other electronic equipment. Air vehicles also have very limited power budgets because of the impact of weight. For both of these environments, the extreme energy efficiency achieved by the SyNAPSE program’s accomplishments could enable a much wider range of portable computing applications for defense."

Neuroscience modeling is another potential application for the SyNAPSE-developed chip. The large number of electronic neurons and synapses in each chip and the ability to tile multiple chips may lead to the development of complex, networked neuromorphic simulators for use in testing network models in neurobiology and deepening current understanding of brain function.

A technical paper on this chip can be viewed here:


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