JTRS-developed PMC speeds implementationProduct
February 04, 2011
Having been tried, tested, and proven to cut JTRS SDR waveform development time, 4DSP Inc.'s AD350 PMC expansion card is vended publicly these days.
Having been tried, tested, and proven to cut JTRS SDR waveform development time, 4DSP Inc.’s AD350 PMC expansion card is vended publicly these days. It is a good fit for MIMO testbed systems and wireless base stations, and it offers prototyping for multi-output and multi-input antenna transmitter system implementation. AD350 can also regulate amplitude voltages in synchrotron systems. So we’re wondering: Does the PMC’s effectiveness come from the pair of Altera Cyclone III FPGAs it houses, or from its dual-channel 14-bit A/D input? Or maybe it’s the 150 MSps maximum sampling rate via its 16-bit, dual-channel, 500 Msps D/A output converter? Who knows. But this thing has so darned much capability that it’s certainly at the head of its proverbial class.
Here’s more: The PMC’s channels are connected to the front panel, while input analog signals utilize efficient AC coupling and wideband transformers at 4.5 MHz to 650 MHz; that serves to lessen phase noise and amplitude distortions. Meanwhile, output analog channels are similarly coupled, but in the 4.5 MHz to 3 GHz range. A front-panel, single-ended SMA connection facilitates an external trigger. (The SMA connection is simpatico with TTL GPS receivers producing 1pps.) Additionally, users can take advantage of the PMC’s flexibility by choosing an onboard or external clock, with the goal of cutting D/A and A/D SNR phase noise degradation and jitter.