DARPA teams up with NSF to develop ASICs tailored for machine learning applications
NewsMarch 25, 2019
ARLINGTON, Va. The Defense Agency Research Projects Agency (DARPA) and National Science Foundation (NSF) are teaming up to collaborate on a new program titled: Real Time Machine Learning (RTML), which seeks to reduce the design costs associated with developing Application-Specific Integrated Circuits (ASICs) tailored for emerging machine learning (ML) applications by developing a means of automatically generating novel chip designs based on ML frameworks.
The goal of the RTML program is to create a compiler – or software platform – that can ingest ML frameworks like TensorFlow and Pytorch and, based on the objectives of the specific ML algorithms or systems, generate hardware design configurations and standard Verilog code optimized for the specific need. Throughout the lifetime of the program, RTML will explore the compiler’s capabilities across two critical, high-bandwidth application areas: 5G networks and image processing.
“A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain,” says Andreas Olofsson, a program manager in DARPA’s Microsystems Technology Office (MTO). “Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. What’s needed is the rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time.”
Based on the application space’s anticipated agility and efficiency, the RTML compiler provides an ideal platform for prototyping and testing fundamental ML research ideas that require novel chip designs. As such, DARPA plans to collaborate with the NSF on this effort.
NSF is pursuing its own Real Time Machine Learning program focused on developing novel ML paradigms and architectures that can support real-time inference and rapid learning. After the first phase of the DARPA RTML program, the agency plans to make its compiler available to NSF researchers to provide a platform for evaluating their proposed ML algorithms and architectures.
During the second phase of the program, DARPA researchers will have an opportunity to evaluate the compiler’s performance and capabilities using the results generated by NSF. The overall expectation of the DARPA-NSF partnership is to lay the foundation for next-generation co-design of RTML algorithms and hardware.
“We are excited to work with DARPA to fund research teams to address the emerging challenges for real-time learning, prediction, and automated decision-making,” said Jim Kurose, NSF's head for Computer and Information Science and Engineering. “This collaboration is in alignment with the American AI Initiative and is critically important to maintaining American leadership in technology and innovation. It will contribute to advances for sustainable energy and water systems, healthcare logistics and delivery, and advanced manufacturing.”
RTML is part of the second phase of DARPA’s Electronics Resurgence Initiative (ERI) – a five-year, upwards of $1.5 billion investment in the future of domestic, U.S. government, and defense electronics systems. As a part of ERI Phase II, DARPA is supporting domestic manufacturing options and enabling the development of differentiated capabilities for diverse needs.
A Proposers Day is scheduled for April 2, 2019. For more information, click here.
Additional details on the RTML program are in the Broad Agency Announcement.
