Military Embedded Systems

Rad-hard SRAM FPGAs enable vast improvements in space exploration


June 01, 2012

As purpose-built Radiation Hard (RH) ASICs fall farther and farther behind in device technology and with their associated development costs and risks spiraling out of control, SRAM-based FPGAs present an ever-more attractive alternative for space applications and systems, also beating out traditional microprocessors and microcontrollers, DSPs, or One-Time Programmable (OTP) FPGAs.

Space environments have high levels of ionizing radiation that create complex design challenges for military systems engineers. Thus, electronic systems used in space must have circuitry that is highly reliable and able to endure extreme amounts of radiation. In space, it isn’t a matter of if electronics will encounter radiation but how much, how often, and how will the device deal with each exposure to radiation. A single charged particle in space can knock thousands of electrons loose, causing electronic noise and signal spikes that can, if unchecked, cause systems to malfunction.

While design and system-level mitigation can ensure the proper operation of military spacecraft and instruments, high reliability and high availability are much easier to achieve with Radiation Hard (RH) components. High reliability is especially critical in systems such as the processing circuitry that runs command and control – the telecommunications system in charge of telemetry to and from ground control where a failure can jeopardize the entire mission. Increasingly, government and private agencies deploying spacecraft are turning to SRAM-based FPGAs to perform these vital processing tasks because their capabilities have dramatically outpaced the traditional custom ASIC or One-Time Programmable (OTP) FPGA approaches.

Rad-hard SRAM-based FPGAs are giving space system designers a compelling set of performance, feature, and flexibility advantages for their new projects. The all-programmable nature of SRAM-based FPGAs enables the capabilities of a system to be improved and expanded even after launch when physical access is no longer possible. The hardware-programmable nature of FPGAs makes them even more flexible than stand-alone processors such as microprocessors, DSPs, and microcontrollers that are only software programmable. What’s more, the largest FPGAs can provide the function of multiple processors and other devices, all on a single chip.

Currently two types of FPGAs are used in space applications: anti-fuse-based one-time programmable FPGAs and SRAM-based reprogrammable FPGAs. Each type of device has its advantages and disadvantages. The anti-fuse-based devices have fewer programmable elements and thus fewer elements that can be upset by radiation. In addition, space-grade anti-fuse devices make extensive use of redundant circuitry. Their relative simplicity and familiarity provide reassurance to space system designers and project managers.

However, like RH ASICs, anti-fuse devices are not available in smaller process geometries such as 90 nm or 65 nm and thus have much lower capacity and performance than SRAM-based devices. SRAM-based devices enjoy a multiple-generation advantage in process geometry, thus offering greater capacity and performance, while consuming less power per gate. SRAM-based devices require configuration each time they are powered-on, and radiation-tolerant, SRAM-based devices may require more extensive error mitigation in the design implementation, such as adding Triple Modular Redundancy (TMR) or error correcting codes.

On the flip side, upset mitigation can be applied selectively where most needed in a reconfigurable FPGA (versus a nonreconfigurable OTP FPGA approach), thus making better use of resources. While configuration at startup adds complexity to the system, it also adds flexibility; last-minute requirement changes and bug fixes can be accommodated even when shortcomings are not apparent until after launch. The Virtex-5QV FPGA reduces the complexity of error mitigation in SRAM-based FPGAs by replacing the traditional 6-transistor configuration memory cell with a rad-hard-by-design, 12-transistor cell that is about 1,000x harder to upset than commercial SRAM cells. Thus, SRAM-based FPGAs are useful in myriad space applications (See Sidebar 1 and also Figure 1).


Figure 1: FPGAs have proven useful in many space applications.

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Sidebar 1: To be useful in space applications, FPGAs must be radiation hardened.

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FPGAs conquer another frontier

It’s difficult to overstate the value an FPGA can offer in a space-bound system application. Once deployed, there is little or no ability to make hands-on hardware changes, so the programmability of an SRAM-based FPGA is a huge benefit. To be sure, microprocessors and microcontrollers can also be reprogrammed. But FPGAs excel in data-flow applications where functions such as packet inspection or signal-processing algorithms implemented in hardware logic offer far more processing throughput than traditional microprocessors. And the FPGA hardware can be easily reconfigured to support new algorithms.

To deploy FPGAs in space applications, however, designers have to understand the environment and learn how to mitigate issues that affect reliability. A number of radiation-induced effects have been identified as a problem area for space-based designs:

  • Single Event Upsets (SEUs)
  • Single Event Transients (SETs)
  • Single Event Functional Interrupts (SEFIs)
  • Single Event Latchups (SELs)
  • Total Ionizing Dose (TID)

Of the radiation effects listed here, the latter two are particularly troublesome because they are destructive; consequently, space engineers require components with proven SEL immunity and large TID margins (2x or 3x) to cover extreme space weather they might encounter. The other three single-event effects might cause temporary malfunctions with varying seriousness depending on the application, ranging from none through annoying all the way to mission loss. SEFIs, though exceedingly rare, can be troublesome: Although recovery may take less than a second, it does require reconfiguring the FPGA with a resultant design outage. Thus, SEFI elimination is highly desirable. Somewhere in the equation, the terms rad hard versus radiation tolerant play a role (see Sidebar 2).

Sidebar 2: ?ad hard?versus ?adiation tolerant?explained.

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In essence, the radiation-hard SRAM-based FPGA has special circuitry to practically eliminate SEUs and SETs. Older SRAM-based FPGAs do not, but they do have error detection hardware that can be used in combination with soft TMR to practically mitigate the effects of SEUs and SETs (see Sidebar 3). The older approach is more complicated for the system designer.

Sidebar 3: Typically design teams have employed Triple Modular Redundancy, a commonly known method for SEU mitigation.

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Boldly going where none have before …

Design teams creating systems for space applications are finding that FPGAs offer numerous advantages over other devices. The hardware and software reprogrammability of SRAM-based FPGAs, zero manufacturing NRE, and vast capacity make these FPGAs extremely attractive for a growing number of space applications. For example, NASA’s highly successful Mars rovers Spirit and Opportunity used SRAM-based reprogrammable FPGAs for critical functions like pyrotechnic firing sequencing during landing and wheel motor control during roving. Using TMR with radiation tolerant SRAM-based FPGAs has allowed design teams to create some amazing systems that are extremely reliable. Now new radiation-hardened SRAM-based FPGAs will allow them to achieve even more remarkable feats and boldly go where no one has gone before.

Gary M. Swift is Senior Staff Engineer for Space Products Development and Radiation Testing, Aerospace and Defense Group, at Xilinx. He is an expert in space radiation effects and single-event testing and worked for almost two decades at NASA’s Jet Propulsion Laboratory before joining Xilinx in 2007. His main responsibility at Xilinx is characterizing complex integrated circuits’ suitability for use in the space radiation environment.

John D. Corbett is a Staff Software Engineer at Xilinx with more than 20 years of experience developing CAD tools for user interface design, education, architecture, computer security, and fault tolerance. At Xilinx, he developed software used to verify Xilinx FPGA designs are suitable for use in Type I cryptographic systems. Prior to Xilinx, he worked at Xerox PARC, Silicon Graphics, and several small startups. John holds seven patents and obtained a BS in Math/Computer Science from Carnegie Mellon.

Xilinx 408-559-7778


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