Direct RF: The transformation of critical defense systemsStory
October 16, 2023
Widespread exploitation of the radio frequency (RF) spectrum profoundly impacts all consumer, commercial, industrial, government, and military markets across the globe. Since defense system counterparts often need hundreds or thousands of antenna elements, they can benefit from the technology and components developed for 5G commercial markets. Because the most critical imperative for government defense organizations is continuous enhancement of electromagnetic spectrum domination, an area of improvement must be enhancing how radio frequency signals of interest are acquired, analyzed, and then exploited through sophisticated signal-processing techniques to deliver an effective response. Such a mandate inspires new defense and electronic warfare (EW) technologies and architectures that boost performance levels across each system.
Judiciously coupling new wideband direct radio frequency (RF) signal data converters with the latest FPGA [field-programmable gate array] devices affords significant critical system performance advantages over previous architectures [for applications such as electronic warfare (EW), radar, and military communications]. Using advanced silicon processes and packaging technologies, device offerings include both discrete monolithic designs and multichip modules. Even so, the fire hose of digitized data samples from these data converters can overwhelm the signal processing resources of even the most powerful FPGAs. To address this issue, key DSP [digital signal processor] resources like digital downconverters are usually incorporated within the direct RF converters. What are some of the new open architecture solutions that incorporate the newer signal acquisition and signal processing resources?
Direct RF for software radio
When the concept of software radio first emerged about 50 years ago, radio engineers immediately recognized its possibilities, even though the performance of existing hardware was limited by two essential elements: the data converter (sampling rate, analog signal bandwidth, and sample accuracy), and the attached DSP system (computational speed, complexity, and accuracy).
Because most RF input signal frequencies far exceeded the capabilities of early analog-to-digital converters (ADCs), such software radios required an RF tuner stage to translate RF signals to lower IF frequencies before they could be digitized. This was often implemented as a traditional heterodyne receiver stage like the one shown at the top of Figure 1.
With ADCs fast enough to digitize RF signal frequencies directly, the RF tuner section shown can be eliminated, resulting in the direct RF receiver shown at the bottom. Without the mixer, local oscillator, intermediate frequency filters, amplifier, and numerous discrete analog components, the RF signal chain is far less complex, bulky, and expensive. Driven by these many benefits for commercial, industrial, and defense markets, performance levels of discrete monolithic direct RF ADCs and digital-to-analog converters (DACs) have steadily advanced, as illustrated in Figure 2.
Because maximum RF signal bandwidths are limited to half the sample rate, the 64 GS/sec ADC shown at the right in the figure can digitize signal bandwidths approaching 32 GHz, covering a vast range of vital military radio applications.
Benefits of direct RF architectures
Phased-array radio systems utilize antennas consisting of multiple elements arranged in linear or planar arrays. Directionality of transmit and receive signal beams is achieved by precisely shifting the relative phase of signals using a dedicated signal processing channel for each element. This setup – which enables a single antenna array to simultaneously track multiple targets in different locations using the same frequency for far more efficient coverage – is widely exploited in defense applications as well as commercial mobile phone systems.
The enormous general market for 5G wireless networks means widespread installation of local, massive-MIMO [multiple-input/multiple-output] phased-array antennas, each typically needing 64 transmit/receive elements. Since defense system counterparts often need hundreds or thousands of antenna elements, they can benefit from the technology and components developed for 5G commercial markets.
Because each element needs its own unique transmit and receive signal, direct RF ADCs and DACs significantly reduce SWaP and system cost of phased-array systems by eliminating the RF frequency translation stages in each signal channel. This dramatically shrinks the size of the electronics housing so it can often fit directly behind the antenna, a major trend in new system architectures.
Direct RF greatly improves the precise channel synchronization between antenna elements by eliminating most discrete analog RF tuner signal components, all subject to component tolerances, aging, temperature drift, reliability, and periodic maintenance.
Direct RF data converters
Most advanced direct RF data converters with sampling rates above 10 GS/sec are available as discrete packaged devices or as silicon die known as “chiplets,” suitable for attaching directly to other die in a multichip module.
In June 2023, Analog Devices announced its Apollo MxFE [mixed-signal front end] family of direct RF ADCs and DACs. A member of this series is the AD9084 featuring four 20 GS/sec 12-bit ADCs and four 28 GS/sec 16-bit DACs using monolithic 16 nm CMOS technology.
With direct RF signal sampling capable of handling signal frequencies up to 18 GHz, the Apollo series now opens up new architectures for many critical Ku band aerospace and defense applications including radar, EW, and communications. Apollo’s on-chip DSP functions include configurable two-stage digital upconverters (DUCs) and digital downconverters (DDCs) for adapting to a wide range of arbitrary RF target bandwidths during deployment. These functions not only reduce data streaming rates to the FPGA, but also eases DSP task loading. Fully synchronous channel operation across multiple Apollo devices supports the growing trend towards large phased-array systems.
Another vendor, Jariet Technologies, has an Electra-MA direct RF data converter chip with two 64 GS/sec 10-bit ADCs and two 64 GS/sec 10-bit DACs. The device also includes on-board DUCs and DDCs, as well as programmable sub-band channelizers for efficiently handling narrowband signals. With a usable analog bandwidth up to 32 GHz for both transceiver channels, the Electra-MA supports Ka-band applications that are becoming increasingly critical for defense systems.
FPGAs for direct RF
AMD’s Versal ACAP [Adaptive Compute Acceleration Platform)] devices based on its 7-nm silicon process consists of a series of six SoC [system-on-chip] architectures, each with specific blends of different processing engines, high band-width memory, and powerful peripherals. (Figure 3.)
The scalar engines include the dual core Arm Cortex-A72 application processor and the dual-core Arm Cortex-R5 real time processor. Unlike most scalar processors that implement single instruction, single data structures, these ARM processors provide single instruction, multiple data (SIMD) operations.
The adaptable engines use programmable logic FPGA fabric plus various types of memory, including block RAM, UltraRAM, and accelerator RAM. Configurable logic in FPGAs is the right platform for real-time state machines, control logic, complex timing, Ethernet packet processing, and synchronization, all essential functions for many embedded defense systems.
Versal offers two types of intelligent engines: The DSP engines are specialized, highly efficient real-time signal processing blocks that include fixed- and floating-point multi-pliers, accumulators, arithmetic units, data multiplexers, and barrel shifters for both scalar and vector data types. With more than 14,000 DSP engines in the largest Versal devices, highly parallelized processing architectures can process real-time data streams from high-rate direct RF data converters. As a result, DSPs deliver the lowest latency of all processing classes.
The second class of intelligent engines is actually two types of AI [artificial intelligence] engines. The general AI engines are balanced to support both machine learning (ML) applications and advanced signal processing for beamforming, radar, FFTs [fast Fourier transforms], filters, video enhancement, and image processing. The AI/ML engines are optimized for ML tasks including image and speech recognition, medical diagnosis, statistical arbitrage, and predictive analytics, and they also offer extended support for ML data types. For ML applications, they are eight times more efficient in silicon area for than DSP engines, reducing power by about 40%.
On-board, flexible high-bandwidth memory (HBM) offer data transfer bandwidths up to 820 GB/sec, representing an 8-time increase in bandwidth compared to traditional DDR5. The upcoming Versal ACAP AI RF series has on-board direct RF ADCs and DACs, following the highly successful theme introduced by RFSoC.
To interconnect all of these diverse resources, ACAP includes an extremely wideband configurable network-on-chip that offers a uniform interface and protocol to simplify system integration. This heterogeneous mix of ACAP resources enables the designer to assign compute power to the processing engine most suitable to the task at hand and the ability to adaptively reassign resources as required. This flexibility of ACAP delivers as much as ten times the performance compared to dedicated processor types alone.
Intel offers two families of direct RF FPGAs, the Stratix 10AX and the new Agilex 9, shown in Figure 4. These multichip modules take advantage of Intel’s chiplet fabrication capabilities to attach various combinations of chiplets to the main FPGA chip using EMIB [embedded multi-die interconnect bridge] and 2.5D packaging processes. The Intel direct RF devices use the Jariet Electra-MA 64 GS/sec 10-bit chiplet data converters for all three of the devices shown. (Figure 4.)
The Stratix 10 AX device uses 14 nm silicon geometry and the FPGA fabric sports 2,753 logic elements, over 11k multipliers, 244 Mbits of on-board RAM, and PCIe Gen3 interfaces. The Agilex 9 devices use Intel’s latest 7 nm process, with 2,693 logic elements, over 17k multipliers, 287 Mbits of RAM, and PCIe Gen4 interfaces. To support high-speed streaming data transport, all devices use 56G PAM-4 and 28G NRZ gigabit serial interfaces.
Direct RF converters/FPGAs
Although the Versal ACAP AI IF series with the integrated direct RF data converters is not yet available, several parts combining the Versal ACAP and interfaces for direct RF data converters are available: the Mercury RFS1140 RF System-in-Package (RFSiP), a multi-chip module combining the AMD VC1902 Versal AI Core FPGA with four 64 GS/sec 10-bit ADCs and DACs using Jariet Electra-MA data converters; the SCFE6933, a space-qualified 6U VITA 78 SpaceVPX card featuring the VC1902 Versal AI Core FPGA and optical I/O, designed for operation in LEO, MEO, GEO, and HEO [low-Earth orbit, medium Earth orbit, geosynchronous Earth orbit, and highly elliptical orbit] satellites and deep-space missions; the SCFE6931 SOSA aligned 6U VPX card with two VC1902 Versal AI core FPGAs with optical wideband optical interfaces to direct RF data converters; and the 5560 SOSA aligned 3U VPX card with the VH1542 Versal HBM ACAP FPGA and mezzanine card site for direct RF data converters. (Figure 5.)
Mercury’s direct RF roadmap extends the 5560 Versal FPGA SOSA architecture with new products that incorporate the new 20 GS/sec ADI Apollo data converters at the front end.
The industry’s first open architecture board using an Intel direct RF FPGA, the early 2023-released Mercury DRF3182, is a 3U Open VPX card featuring the Stratix10 AX device. It has four transceiver channels of direct RF digitization and generation at 51.2 GS/sec covering a frequency band of 2 to 18 GHz to support numerous EW applications. Eight PCIe Gen3 x4 data plane ports deliver 64 GB/sec of data across the backplane to other cards. (Figure 6.)
Mercury is currently developing several roadmap products based on Intel Agilex 9 devices to speed adoption of this new technology for open architecture embedded computing boards for deployed systems.
Direct RF for defense applications
Direct RF architectures boost performance of embedded systems for defense applications in many ways by eliminating the analog RF frequency translation stage, reducing latency, minimizing analog phase and amplitude uncertainties, and simplifying channel synchronization. Virtually all direct RF data converters contain dedicated digital frequency translators (both DDCs and DUCs) to provide much faster tuning across a very wide frequency span to support complex sweeping and hopping patterns, a critical advantage for many advanced countermeasure and EW algorithms.
The powerful heterogeneous processing resources of the latest classes of FPGAs discussed above provide a flexible choice of processing engines best suited to the wide range of required tasks including AI, ML, decoding, demodulation, decryption, signal classification, image processing, sensor fusion, target recognition, trajectory calculations, fire control, countermeasures, attack plan development, and many more. These processor task assignments are adaptable during a mission to optimize performance.
Because legacy scanning receivers sequentially sweep across a span using slower analog RF tuners, they can easily miss transients outside of the current scan window. Direct RF receivers can not only stare across a much wider scan window, but can also instantaneously step to a new window, thus missing far fewer transients. When signals of interest are detected, a bank of narrowband DDCs can zoom in on them for further exploitation.
Direct RF phased array countermeasure systems can take advantage of this flexible wideband/narrowband capability to operate multiple narrowband DDCs in parallel, each tuned to specific target frequencies located anywhere across the entire frequency span, and beamformed to specific target directions.
As discussed earlier, direct RF data converters and FPGAs must be tightly coupled for best overall performance. As a better alternative to JESD (standard) serial interfaces, the latest chiplet bonding techniques can stream data across wide high-speed parallel buses within a single multichip module.
Flexible chiplet packaging affords much shorter development cycles of new system-in-package offerings containing FPGAs, direct RF data converters, and other specialized peripherals tailored to specific applications and platforms. Such varied offerings of advanced silicon and packaging technologies ensures a growing wealth of deployable capabilities clearly transformative to defense systems.
Rodger Hosking is vice president, Mercury Systems Mixed Signal. Rodger has more than 30 years in the electronics industry and is one of the co-founders of Pentek; he has authored hundreds of articles about software radio and digital signal processing. Prior to Pentek, he served as engineering manager at Wavetek/Rockland, and he holds patents in frequency synthesis and spectrum-analysis techniques. He holds a BS degree in physics from Allegheny College in Pennsylvania and BSEE and MSEE degrees from Columbia University in New York.