Military Embedded Systems

Is high-performance electronic warfare compatible with open standards?


January 18, 2023

Robert Normoyle

Herrick Technology Laboratories

Image by pikisuperstar/Freepik

Today, multiple agencies are involved in open architecture standards to ensure that weapons and defense system features match up with their perception of future systems specified and beginning to be used by the U.S. Department of Defense (DoD). Examples of key attributes provided by these standards relevant to electronic warfare (EW) are the VPX backplane profiles and MORA/V49.2 protocols. The DoD has had a hand in developing both of these in order to specify and develop reference architectures to verify performance.  

Prior to the promulgation of the SOSA [Sensor Open Systems Architecture] framework, systems integrators based their designs on a standard such as VPX, VXS, or VME, and declared their open architecture, though at that time there wasn’t a robust system level specification to enable interoperability of 3rd-party components. The standards provided mechanical and high-level signal type definitions, leaving designers with a lot of leeway on signal protocols. Often the backplane, the board interfaces, and the data protocol interfaces were proprietary. Even though the designer could state the design as open architecture, the Modular Open Systems Approach (MOSA) goals were not effectively achieved – namely, the goals of interoperability, scalability, competition, faster refresh, and lower cost.

This disconnect was even more prevalent with high-performance electronic warfare (EW) systems, since the coordination between components and systems is expected at a nanosecond scale and extreme frequency coverage. A stretch goal instantaneous frequency coverage has been 2 to 18 GHz, 16 GHz of instantaneous bandwidth, for electronic surveillance (ES), electronic attack, and digital RF memory (DRFM) capabilities. In addition to this range, banded capability at millimeter frequency was also desirable. Even though government agencies specified MOSA-based approaches, there was no technical detailed description of what this meant and how to verify it. The architectures were so intricately interdependent upon custom designs that changes could only be done by original equipment providers. The government agencies were still tied to a single source for simple upgrades to an architecture, resulting in simple changes to designs costing millions.

Do standards really support interoperability?

The pioneer computer programmer Grace Hopper coined the phrase: "The nice thing about standards is that there are so many of them to choose from”, implying that the use of standards is not effective, and every organization may “choose” to use something different, thus negating interoperability.

This statement has been a typical pushback about hewing to standards, though over the last five or 10 years there has been a convergence between DoD organizations and industry. Examples of this convergence are the CMOSS [C4ISR/Electronic Warfare Modular Open Suite of Standards], SOSA, and CMFF [CMOSS Mounted Form Factor] efforts, which have been using the best attributes of multiple standards such as VPX, VITA49, MORA [Modular Open RF Architecture], VICTORY [Vehicular Integration for C4ISR/EW Interoperability, FACE [Future Airborne Capability Environment], and HOST [Hardware Open Systems Technologies] to develop a framework that is being adopted by a majority of the suppliers and becoming required by more and more DoD programs. These interfaces have been designed by a consortium of industry, government, and academia engineers who are vetting the proposed architecture components with their real-life experiences of EW, signals intelligence (SIGINT), radar, and communications systems requirements. This situation is a key difference from how standards were developed a decade earlier, at which time the primary drivers were just industry with very little government involvement.

Can standards really support high-performance EW requirements?

In the early days of digitized audio – namely the 1980s – a similar problem existed, as custom cards were needed to compress/expand audio signals. As personal computer (PC) technology evolved, it became viable to use software-based encoder/decoders on the processors as opposed to using custom hardware solutions. This maturation was an enabler for the development of audio and video compression software that provides interoperability across platforms, whether Mac or PC, at a low cost and with very little effort by the user. When programmable technology approaches the performance to directly process the signal phenomena of interest, then open architecture approaches and standards are viable.

Today we have arrived at a point where the latest processors used for EW analytics and jamming can directly ingest, manipulate, and create jamming waveforms over ultra-wide bandwidths. These processors include FPGAs [field-programmable gate arrays] for front-end processing and detection. An EW system can provide frequency coverage of 16 GHz of instantaneous frequency coverage and also provide nanosecond precision control, status, and IQ data interfaces via SOSA standards.

A similar matured situation exists today: Capabilities of software-defined radio (SDR) have reached the information processing rate needed to handle multiple gigahertz of bandwidth. A two-slot 3U VPX card can provide simultaneous transmit and receive capability of 4+ GHz. Multiple copies can be integrated into a SOSA chassis to provide 16 GHz of coverage, such as in a range of 2-18 GHz.

Today, backplane architectures are available that can convey over 200 Gbps of data as GbE and PCI per slot, which is sufficient to convey 4 GHz of data each direction. MORA/V49.2 interfaces provide timestamped high-precision information including IQ data packets, control packets, and status packets between modules and systems. This protocol, combined with the 1 PPS and 100 MHz reference clocks in a system architecture, makes it possible to achieve nanosecond precision. The standards bodies continue to progress efforts to make the standards synergistic and move forward with new enhancements to support emerging technology. New VPX connectors are being defined that support bandwidth of 800 Gbps per module, which is sufficient to convey 16 GHz of instantaneous bandwidth at 16 bits resolution.

Interoperability advantages of SOSA standard for EW solutions

The SOSA standards group consists of more than 100 organizations and more than 1,000 members, all working to proactively develop an interoperable framework for multiple-intelligence (multi-int) applications. EW engineers are part of this group and voice their expertise to mold the standard to meet demands of high-performance EW. The consortium also takes into account the other modalities of operation including communications, radar, and SIGINT. The resulting standards have enabled companies to build products based on the standards, anticipating that multiple DoD programs can leverage them.

This alignment reduces the time and schedule of acquisition programs because the chassis and the modules are being developed in advance of the acquisition cycle, rather than during the program’s NRE phase. This reality is quite different from legacy acquisitions where chassis were typically custom-designed for an acquisition effort, with commercial off-the-shelf (COTS) modules typically needing modification to support the customization required by the prime. Today, a chassis built for one program is being rapidly deployed for another.

This same phenomenon is also true for VPX modules, where modules from a variety of vendors can be used in multiple chassis. Figure 1 shows the number of combinations viable in four and eight SOSA payload slots, based on 1 to 20 unique payload cards, such as EW SDR. The combination with repetition formula was used as shown. The repetitions do not include the same cards configured differently in a chassis. The maximum number of SDR modules is based on a quick survey of vendors at the 2022 Association of Old Crows Annual International Symposium and is a conservative number.

[Figure 1 | Table shows the number of configurations in a chassis as a function of card types and number of slots in a chassis.]

The number of configurations is staggering, perhaps not all of them uniquely beneficial, though if only 10% are deployable architectures, it is still an impressive number of configurations compared to the single-purpose chassis of the past since it could provide dozens of architectures ready for redeployment for different missions and platforms. It was unprecedented in legacy EW architectures to reuse modules and chassis for multiple configurations for multiple programs and platforms that are not just EW focused, but multi-int. Companies are seeing the phenomenon in the integrations of SOSA aligned chassis and SIGINT/EW VPX modules. This situation enables SDR modules from multiple vendors to be used in multiple chassis for a diversity of programs and products providing fully integrated solutions can employ modules from multiple performers.

FPGA partial reconfiguration enables multi-int capability

The framework and interfaces for a generic mission manager which can support SDR reconfiguration is a being defined by SOSA. Just as there were many ways a chassis can be configured with different SDR modules, there are also many ways that the SDR cards can be dynamically configured to support different mission requirements at the depot or to dynamically change the SDR capability of the chassis in situ of a mission. There are three high-level use cases:

1.       A SOSA chassis built for a specific EW program is redeployed to support a different EW program and/or another operational mode such as SIGINT or radar

2.       SOSA chassis reconfigured at the depot with an alternate mission-specific card set 

3.       SOSA chassis dynamically reconfigured in situ to support different modalities of operation

An example of repurposing a notional SOSA chassis payload cards is shown in Figure 2 and 3. In Figure 2, the chassis provides a total of 16 GHz of ES and EA capability by configuring each of the eight payload slots with 2 GHz IBW [instantaneous bandwidth] UWB [ultra wideband] SDRs providing a 20 MHz to 20 GHz frequency coverage. In Figure 3, the same chassis is reconfigured at the depot to provide eight channels for instantaneous precision DF [direction finding] and eight channels for ES [electronic support]. The same chassis provides a high precision interferometer DF while simultaneously providing 8 GHz IBW of frequency coverage.

[Figure 2 | Notional chassis configuration consisting of eight payload slots providing 16 GHz IBW, each with a 20 MHz to 20 GHz frequency range.]

[Figure 3 | Notional chassis depot configuration consisting of four payload slots providing instantaneous DF capability and four payload slots providing 8 GHz IBW, each with a 20 MHz to 20 GHz frequency range.]

An example of dynamically reconfiguring a chassis in situ is presented in Table 1. For this notional example, the chassis is configured as shown in Figure 2. It has eight SDR cards each with 2 GHz IBW which can be dynamically configured for different operations during the mission. During the start of the mission, it is in Mode 1, utilizing all the channels for ES providing 16 GHz of IBW surveillance. As it detects targeting threat radar, it moves to Mode 2, reallocating ES channels for a look-thru jamming technique while still maintaining 14 GHz IBW for ES. When a missile-targeting radar is detected, it moves to Mode 3, by dynamically reloading firmware and bonding channels coherently together to form a digital RF memory (DRFM) jamming channel. While in this mode, there is still 10 GHz of instantaneous BW ES capability. To determine the effectiveness of the EW technique, it switches to Mode 4, reconfiguring UWB SDR 4 and 5 to create a UWB radar. As mentioned earlier, this is a notional representation of one scenario to represent the potential value of dynamic in situ mission management. Many other dynamic configuration usages exist.

[Table 1 | Shown is a notional example of dynamic reallocation of SOSA SDR payloads throughout an EW mission.]


RF and FPGA technology – SOSA aligned for EW

HTL’s UWB SDR module and 19-slot chassis capability is based on the HTLv-43 (RF converter) and HTLv-53 (digitizer + FPGA) which provides a total of 4 GHz of full-duplex simultaneous capability with a frequency range of 20 MHz to 20 GHz. The modules provide four 2 GHz RF tuners: two receivers and two exciters. Each of the channels are independently tunable, though can be made phase-coherent to one another and across multiple cards. The superheterodyne architecture enables the necessary selectivity when operating in congested and/or contested dynamic RF environments.  (Figure 4.)

[Figure 4 | Shown is the HTLv-53 digitizer plus FPGA.]

HTL provides both an 11-slot and 19-slot chassis aligned with SOSA release 1.0. These chassis can support dozens of configuration options. With the HTLv-43/53 cards they can support the UWB configuration capabilities presented. With the HTLv-43/53 cards, the 11-slot provides 8 GHz of IBW for both ES and EA or DRFM capability, whereas the 19-slot provides 16 GHz of the same type of capability. The frequency range for each chassis can be extended to 44 GHz with the use of HTL44E frequency extender.

Robert Normoyle is the Director of Open Systems at Herrick Technology Laboratories (HTL), where he leads the development SOSA/CMOSS-based modules and chassis. Mr. Normoyle has more than 40 years of experience developing high-performance EW, radar, and SIGINT systems. He began his career at NRL and has worked at several SDR companies including L3 and DRS. He also worked at Johns Hopkins University Applied Physics Laboratory providing technical guidance to multiple programs for the Navy, ONR, Army C5ISR, and DARPA. He led the APL’s contributions to the V49.2 standard and VPX profiles, which are foundational for the CMOSS and SOSA standards. Readers may reach the author at [email protected].

Herrick Technology Laboratories · 

Featured Companies