FPGA Design Software Suite
Eletter Product
Blue Pearl Software enables “RTL Signoff for FPGAs,” says Gary Smith, EDA Analyst. We invite you and your colleagues to check out all the benefits of the Blue Pearl Software Suite.
Our Blue Pearl Software Suite has been fine tuned to address important design issues.
These include:
- Addressing timing closure
- Generating the right constraints automatically
- Using existing FPGA libraries to improve analysis
- Offering pre-synthesis longest path analysis
- Analyzing FPGA resources for implementation using optimum levels of logic
- Using a new grey cell methodology to enable full-chip CDC analysis and inter-IP block analysis
The Blue Pearl Software Suite also runs on Windows, is easy to use, is priced right, accelerates RTL signoff, supports SystemVerilog, and works with design flows supported by Xilinx and Synopsys.
Learn more about our FPGA design benefits.
About Blue Pearl Software
The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows. Our solution includes linting, CDC analysis, and automatic SDC generation. With our SDCs, we automate the synthesis and place and route phases of FPGA design implementation. Our software reduces iterations and overall design time, and our Visual Verification Environment™ makes it easy to use for any level of FPGA designers.
Our collaboration with Synopsys offers an optimized flow that works with Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can automatically generate an exhaustive set of constraints that address false and multi-cycle paths and work with Synopsys' synthesis flow.
