PRODUCT OF THE WEEK: Mercury Systems' SOSA aligned, 3U VPX, high-speed data converter for radar applications

This week’s product, the Mercury Systems’ SOSA aligned Jade 5585 250 MHz A/D with Virtex UltraScale+ HBM FPGA - 3U VPX board, is an 8-channel, high-speed data converter with programmable DDCs (digital downconverters). It is suitable for connection to HF or IF ports of a communications or radar system. Its built-in data capture feature offers a turnkey solution as well as a platform for developing and deploying custom FPGA-processing IP.

Ample data transfer bandwidth and flexibility are provided by a range of board interfaces including 1 GigE, 10 GigE, 40 GigE, dual 100 GigE and PCIe with installation of Mercury or user-supplied IP. The Virtex UltraScale+ HBM’s on-chip high-bandwidth memory coupled with the FPGA’s logic and DSP density enable the model 5585 to be a single-slot SOSA aligned 3U VPX data acquisition and processing powerhouse.

Xilinx Virtex UltraScale+ HBM FPGA

The 5585 features the VU37P Virtex UltraScale+ HBM, which has 8 GB of on-chip HBM SDRAM supporting memory bandwidth of as much as 460 GB/s. This represents better than a 20X throughput increase over traditional, external DDR4 SDRAM. This increased performance addresses the ever-accelerating memory requirements of high bandwidth, high computation applications. Additional resources include 9024 DSP slices, 2.8 million system logic cells and 32.7 Gb/s GTY gigabit serial transceivers.

ARM Processor

The Jade 5585's on-board ARM processor provides a path to reprogram the FPGA through 1 GigE. This is ideal for applications that might need to dynamically change FPGA functionality during deployment. The processor runs Linux.

Board Architecture

The 5585 board design places the Virtex UltraScale+ FPGA as the cornerstone of the architecture. The FPGA has access to all data and control paths, enabling factory-installed functions including data multiplexing, channel selection, data packing, gating, triggering, and memory control. The Jade architecture organizes the FPGA as a container for data-processing applications where each function exists as an intellectual property (IP) module.

A/D Converter Stage

The front end accepts eight analog HF or IF inputs from the VITA 67.3 C connector with transformer coupling into four Texas Instruments ADS42LB69 dual 250 MHz, 16- bit A/D converters. The digital outputs are delivered into the Virtex UltraScale+ HBM FPGA for signal processing or routing to other module resources.

A/D Acquisition IP Modules

The 5585 features eight A/D Acquisition IP Modules for easily capturing and transferring data. Each module can receive data from any of the eight A/Ds, or a test signal generator and move the acquired data off board over 10 GigE, 40 GigE, or PCIe. For each transfer, the acquisition module can automatically construct metadata packets containing A/D channel ID, a sample-accurate time stamp, and data length information. These actions simplify the host processor’s job of identifying and executing on the data.

Integrated Platform Management Controller

The 5585 uses an Integrated Platform Management Controller (IPMC) to provide a fully compliant and flexible management solution for Field Replaceable Units (FRU) that support the VITA 46.11 standard required by Hardware Open Standard Technologies (HOST) and SOSA architectures. The IPMC provides a standardized implementation of FRU management interfaces, control signals and sensor monitoring.

Features

Exceptional dynamic range and analog signal integrity
Eight 250 MHz 16-bit A/Ds
Optional VITA 67.3C optical interface for backplane gigabit serial communication
Compatible with several VITA standards including: VITA 46, VITA 48.11, VITA 67.3C and VITA 65 (OpenVPX™ System Specification)
Navigator Design Suite for software and custom IP development: Environmental Option -763: L3a (conduction-cooled)
- Operating Temp: 0° to 70° C
- Storage Temp: -50° to 100° C
- Relative Humidity: 0 to 95%, noncondensing