Military Embedded Systems

Ethernet-based precision timing enables real-time distributed military systems


September 14, 2010

Steve Yates

ADI Engineering

Precision timing is critical in networked real-time military applications. Recent advances in Ethernet technology provide standards-based precision timing and synchronization to developers of networked wireless communications, radar, multimedia, and other networked real-time applications. The IEEE 1588 Precision Time Protocol enhances Ethernet to deliver timing accuracies in the nanosecond range over standard COTS network infrastructure.

Submicrosecond timing and synchronization are critical to many military electronic systems that encode, decode, transport, or present real-time data in applications such as weapons test systems, distributed sensor networks, radar processing, signal intelligence, distributed RF systems, and IP-based multimedia. Synchronization of multiple distributed devices is a major challenge facing today’s military systems developers.

With Ethernet’s rapid growth as a networking technology for real-time embedded applications, new industry standards are now emerging to add precision timing to Ethernet itself. The following discussion provides an overview of the challenges facing real-time military applications developers and the standards-based approaches that are becoming available to assist them. These new network-based precision timing standards use COTS technologies to improve timing accuracy while reducing cost. The following discussion also focuses on the IEEE 1588 Precision Time Protocol, which enhances Ethernet to deliver timing accuracies in the nanosecond range over standard COTS network infrastructure.

The need for network-based timing and synchronization

The venerable Network Time Protocol (NTP) provides Time Of Day (TOD) updates to networked devices. NTP, however, only provides TOD information accurate to human levels of perception – from hundreds of milliseconds to seconds. Real-time applications often require timing accuracies 1,000 to 1,000,000 times better than NTP.

Until recently, distributed precision timing solutions available to developers have included separate cables or extra hardware at each device to provide precision clocks, such as IRIG-B or GPS receivers. But these approaches entail substantial challenges in development effort, equipment complexity and cost, and timing accuracy or system topology.

Ethernet-based timing and synchronization is standardized

Ratified in 2002, IEEE 1588 Precision Time Protocol (PTP) is a standardized Layer-2 and -3 method of submicrosecond synchronization across LANs. IEEE 1588 PTP is a master-slave protocol, where one or more slave devices synchronizes with multicast timing messages sent by a PTP clock grandmaster. PTP is a low-overhead protocol and is compatible with standard COTS network infrastructure, while requiring no new cables.

More recently, the IEEE 802.1as draft standard (one of three from the A/V Bridging Task Group) has been proposed as extending IEEE 1588v2 PTP for synchronization across Ethernet in LAN and WAN environments. IEEE 1588v2 was ratified in 2008, and IEEE 802.1as was developed as a simplified profile intended for multimedia applications, and is reusable in many other applications. IEEE 1588v2 makes several improvements to the original IEEE 1588 standard aimed at improving accuracy and reducing costs. 802.1as also extends PTP to other network technologies not specifically addressed by IEEE 1588, such as 802.11.

Synchronous Ethernet (SyncE) is an alternate approach to network-based synchronization that transports precision clocks via the Ethernet PHY layer interfaces. SyncE provides a network-wide Layer 1 synchronization capability similar to SONET/SDH.

The Layer 1 approach taken by SyncE makes its accuracy potentially better than PTP. However, the additional physical layer implementation requirements of SyncE render it largely incompatible with standard COTS Ethernet infrastructure such as routers, bridges, and switches.

How PTP works

Figure 1 shows a simplified series of timing messages between a PTP master and slave, used to estimate the total master/slave clock offsets and network latencies so that slaves may sync up to the master’s clock. A PTP slave needs two pieces of information for synchronization: (1) how much its clock is offset from the PTP master, and (2) the network propagation delay. Slaves are given periodic opportunities to measure their clock offset when the PTP master sends Sync multicast messages with a master time stamp T1. PTP masters without dedicated IEEE 1588 packet time stamping hardware often do not exactly know T1 when transmitting the Sync message, so they send T1 in an optional Follow-up message. PTP slaves time stamp the Sync and Follow-up messages with their local clock upon receipt (T2), and from that they compute their total clock offset from the master.


Figure 1: Simplified IEEE 1588 PTP synchronization messaging

(Click graphic to zoom by 1.4x)




PTP slaves initiate network latency estimates when they send a Delay Request message (T3). The PTP master records its time stamp T4 upon receipt of the Delay Request, and sends a Delay Response also time stamped with T4. Use of T4 as the Delay Response time stamp removes the master’s processing latency from the measurement, allowing the slave to measure the round-trip time across the network accurately, and in turn allowing it to estimate the one-way network latency. Note that the PTP network latency measurement algorithm assumes the network latency is symmetrical.

IEEE 1588 PTP typically updates the latency estimation process once a second, but IEEE 1588v2 allows the frequency of this process to increase to as high as 30-40 times a second for improved accuracy. The Delay Request/Response sequence typically is performed less often, since it is assumed that network latencies remain relatively stable with time.

PTP is effective

For military systems developers, PTP has many significant advantages over previous synchronization methods, such as IRIG-B. Primary among these is the concept of “no new wires,” since PTP utilizes standard cabling and works with existing Ethernet connector interfaces, simplifying systems and reducing the cost of development, installation, and operation. Additionally, PTP brings nanosecond-level accuracy, up to 1,000x better than IRIG-B, and can null out timing skews introduced by the network itself, offering large potential increases in system-wide timing accuracy.

While IEEE 1588 PTP packet time stamping and classification can be implemented purely in software, achieving the best timing accuracy requires dedicated packet classification and time-stamping hardware to avoid introduction of software-related timing variances. PTP-enabled Ethernet MACs time stamp all TX and RX packets as close to the wire as possible, based on a high-frequency timebase. From this, precision timing can be recovered anywhere on the LAN to accuracies down to the nanosecond range, depending on the implementation.

A simplified PTP implementation using hardware time stamping is shown in Figure 2.


Figure 2: Simplified IEEE 1588 PTP stack with hardware time stamping

(Click graphic to zoom by 1.3x)




IEEE 1588 is COTS

The good news for military developers is that PTP is increasing in popularity and more COTS PTP-enabled devices are coming to market: Ethernet NICs, Single Board Computers (SBCs), components such as Ethernet MACs, and PTP software stacks.

COTS PTP NICs include the National Instruments PCI-1588, the Oregano Systems syn1588, and the Meinberg PTP270PEX. Meinberg also outfits the PRP270PEX and some of their other PTP products with IRIG outputs, allowing IRIG devices to synchronize via PTP. This provides an incremental upgrade path to PTP, without requiring the wholesale replacement of all legacy equipment.

Embedded SBCs with onboard PTP support include ADI Engineering’s extended temperature and fanless Cinnamon Bay SBC (Figure 3), based on the low-power Intel Atom Z5xxP processor and the Ocracoke Island SBC based on the Intel EP80579 integrated processor.


Figure 3: The Cinnamon Bay SBC based on the Intel Atom Z5xxP with IEEE 1588 and 802.1as hardware support from ADI Engineering

(Click graphic to zoom by 1.2x)




Intel, Marvell, Broadcom, and National Semiconductor offer Ethernet MAC silicon providing hardware-based PTP packet time stamping and classification. Available products include single- and multi-port gigabit and 10 GbE chips.

A growing number of microprocessors also provides PTP hardware support. Examples include the EP80579, IXP465, and IXP435 from Intel, the Octeon II processor family from Cavium, and the ColdFire, PowerQUICC II Pro, and PowerQUICC III families from Freescale. The Intel EP80579 not only provides packet time-stamping hardware, but it also implements a variable frequency system clock that synchronizes all system-level timing to the PTP master within 15 ns. And it is available in an extended temperature version.

IEEE 1588 PTP and 802.1as: Software support lags

A major issue facing developers looking to use PTP is the sparse support in OSs and software drivers. Even when PTP packet time stamping and classification are performed in hardware, the upper layers of the PTP protocol rely on third-party middleware that must be purchased and integrated, or home-grown code that must be developed. COTS PTP middleware is currently available from vendors including IXAAT, Real-Time Systems, and Quadros Systems.

Next steps for PTP

As tightly synchronized distributed military systems increasingly turn to industry standard networking technology such as Ethernet, PTP offers developers an attractive precision timing and synchronization solution. Military system developers today must weigh the implementation requirements of PTP versus the potential reductions in cost, complexity, cabling, and weight as compared to alternative techniques. Fortunately, with the quickly growing and broad-based commercial and military demand, PTP support should continue to improve. PTP is poised for continued growth, and this is an exciting technology that military system developers should continue to monitor closely.

Steve Yates is CTO at ADI Engineering, a U.S.-based original design manufacturer providing turnkey design-through-production services under an “Open IP” model. He previously worked as a hardware engineer for GE Fanuc and Intel Corporation. Steve graduated with a BS and MS in Electrical Engineering from the University of Virginia, and is a registered Professional Engineer in the Commonwealth of Virginia. He can be contacted at [email protected].

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