Military Embedded Systems

SBCs move beyond traditional roles in embedded architectures


April 19, 2012

Doug Patterson

Aitech Defense Systems

Advances in IC density as well as the advent of new, low-power processors have enabled embedded designers to rethink the traditional role of the SBC within embedded military applications. With more functionality being housed on fewer components, valuable space is freed up on the board itself, allowing for deeper SBC integration within complete, fully functioning embedded computing subsystems.

Time is money, and in embedded military applications under fire from budget cuts from sequestration, stalled programs, and aging technology, never has a statement been more true. Those system programs that thrive will be the ones that take advantage of the lower Size, Weight, and Power (SWaP) of today’s embedded components and subsystems while successfully integrating network architectures at both the hardware and software levels.

One computing area in particular where this change is taking place is Single Board Computers (SBCs), especially in ground and airborne military systems. Manufacturers have begun to look beyond traditional SBC roles to see how embedded computing systems can benefit from the overall technological advancements within the industry.

Instead of merely incorporating the latest iteration of a processing technology or of a smaller, denser IC, companies are taking a step back and looking to see what else can be done from an overall board, and even system, perspective.

Moore’s Law is nothing new; circuits have been doubling in density and decreasing in size for years. The truly revolutionary part is that as the decrease in component size has allowed integrating several chips into just one, tremendous amounts of real estate have been freed up on the SBC.

And what is a designer to do with that extra space left on a board? Add more functions that couldn’t previously be placed on the board, of course. This has enabled an SBC to move beyond its place as a mere component in a system that housed the processor and memory chips to an integral system component that is far more capable than its standard definition.

But the price to pay with all these added I/O features is that there are no backplane I/O pins to bring these functions off the SBCs. This means that new and updated industry mechanical and bus protocol standards are needed to keep up with the compression pressures from the silicon and board vendors.

The trend is clear: As more functionality is pulled onto SBCs, deeper integration at the subsystem level becomes more easily obtainable. The SBC can now handle many of the computing functions that could not be housed on the board before, including lots more on-board memory, I/O functions, interfaces, and control logic.

In fact, today’s systems and platform integrators are quickly realizing that they are no longer tied to traditional embedded computing SBCs, backplane architectures, and system slots; they can house all this functionality on one small subsystem that can be integrated onto one board, housed directly in a stand-alone, rugged small form factor enclosure.

Deeper integration of the SBC

SBCs are now moving further into the embedded computing integration process, becoming the central component in fully integrated subsystems. The board itself is now the keeper of far more system functionality than ever before.

In fact, IC density and package size have decreased so much that it is no longer the dimensions of the components that are driving the size of a military embedded system. Instead, overall size is now determined by the larger, rugged connectors required on the chassis/enclosure front panels. These larger connectors are needed to interface with the connector harnesses of many legacy platforms, which are currently under a technology-insertion, capabilities (or Spiral) upgrade program.

As the density of embedded components – and, therefore, SBCs – increases, there is a shift in how an SBC functions within an embedded computer. Smarter components equate to more intelligent systems that can now provide unique attributes to mission-critical computing, such as platform location monitoring built into the onboard FPGA of an I/O expansion unit, with a highly dense SBC at the core. This helps in terms of both form and function, since more functionality is contained within a smaller, compact overall system.

How low can you go?

With the recent technology and machine control precision advances in Direct Step on Wafer (DSW) hyper-Numerical Aperture (NA) immersion lithography now edging below 22 nm, continual die shrinks as seen in today’s Very Large Scale Integration (VLSI) ICs are constantly tugging on Moore’s Law (Figure 1).


Figure 1: Projected line geometries in semiconductor manufacturing near 4 nm within the next 10 years.

(Click graphic to zoom)




This enhanced capability is benefiting SBCs by advancing the general availability of multi-GHz, multicore processors with dedicated integrated instruction and data caches, fat pipe fabric crossbar switches of high-speed serial lanes to high-speed memory buses, and on-chip real-world I/O.

These improvements to raw processor and memory access make the trade-offs of speed and performance less burdensome versus (instruction and data) clock cycles. It is now much easier to implement in software what was once rooted in the base silicon only a few years ago.

The new raw and enhanced performance allows SBCs to house non-generic control systems like digital signal processing, data security, and “on-the-fly” advanced “trusted platform” Data Encryption Standards (DES) and data cryptography. The trends and advances in this area that go above, and well beyond, the 128-bit portable encryption keys traditionally in use today are clearly seen on the horizon.

Balancing the benefits of COTS

Because they reduce overall design and integration time, COTS products continue to provide a cost-effective means of easily integrating advanced technologies in embedded systems, especially when implemented by manufacturers familiar with the nuances of military, defense, and aerospace applications.

In light of the state of many current military programs, COTS still provides a cost- and schedule-effective means to update technologies in existing programs, particularly in avionics and vetronics. However, power consumption and heat dissipation still remain large issues in these areas.

COTS-based SBCs primarily utilize multicore RISC and Graphics Processor Unit (GPU) processors from three main industry sources: Freescale, Intel, and AMD. These processors are surrounded by heaps of super-fast caches, fast DDR “X” SDRAM, serial fabric pipelines, and loads of platform-relevant I/O, all packed onto a single 3U or 6U Eurocard with daughterboard interconnect buses like VMEbus, CompactPCI, or OpenVPX and standard mezzanines.

The natural outcome – or side effect – of these larger SBCs with their 2+ GHz VLSI RISC and GPU processors is much higher power consumption, creating significant heat generation. It’s not uncommon for these processors alone to dissipate well over 60 W. Add memory, I/O, and ancillary support circuitry for these boards, and dissipation can quickly reach over 100 W per backplane slot.

While an SBC can use new and clever heat removal methods, such as a copper-aluminum hybrid thermal frame, there’s an associated cost and power density load put on the overall housing of these power-hungry processors and the subsystem boards they reside upon; this forces more costly liquid and direct impinged, spray-cooling solutions.

ARM lends a hand for military system designers

The best solution overall would be to minimize heat generation on these tightly packed SBCs from the start, eliminating the need for additional system cooling techniques. Encroaching quickly into the embedded computing space are ARM single- and multicore processors.

These processors provide the equivalent raw processing horsepower as other more high-power processors currently used on military embedded SBCs, but with advanced and sophisticated on-chip and on-board power management; thus, they dissipate only 1/50 to 1/100 of the power of the larger VLSI RISC and GPU devices.

With these new ARM processors on next-generation SBCs and Data Concentrator Units (DCUs), imagine what a distributed and networked cluster of these remote interface/remote I/O engine nodes could do spread around tomorrow’s military ground, air, or space-based manned and unmanned robotic vehicles.

Look closely at the latest smartphone to witness firsthand the power and capability of these ARM-based single core and multicore machines. Today’s Android or iPhone contains enough raw processing performance to not only provide a full-featured cell phone, but also provide dual multimegapixel digital cameras and a high-definition video camera, a highly functional user touch interface, an HD display, and myriad other features – now too numerous to all be listed here.

Along with all this, and while carrying 64 GB of memory, these processors:

  • Execute all the individual video and audio codecs and modems needed for GPS, WAN, Bluetooth, and WiFi wireless;
  • Conduct real-time monitoring of internal three-axis accelerometers and gyros, field intensity, and Hall effect sensors (for relative and absolute global positional and situational awareness);
  • Directly manage all compression and decompression algorithms; and 
  • Operate an MP3 audio player, still and video camera, Web browser, and so on.

The list goes on, and this raw horsepower can run for several days on a battery pack measuring a volume of less than 0.5"3 and is barely warm to the touch, even under the heaviest usage and loading.

The military applications that will benefit from these low-power processors are as endless as the imagination of the engineer emboldened with the charter to use this new and exciting technology.

Integrated SBCs provide needed SWaP advantage

High-performance SBCs are stepping up to meet the challenges of today’s and tomorrow’s military and avionic Remote I/O (RIOs), DCUs, and Rugged Computer Units (RCUs) (Figure 2). These systems can marry ultra-high-power, super-performance SBCs with the super-low-power ARM-based RIOs, giving designers one fully functioning system.


Figure 2: Units such as Aitech’s A175 and NightHawk RCU are bridging the gap between ultra-high-performance SBCs and extremely low-power RIOs.

(Click graphic to zoom by 1.9x)




And, the miniature scale of microelectronics today is displacing traditional architectures, enabling the SBC functionality to reside in one large FPGA, rather than require a separate board.

Take, for example, a networked, FPGA-based DCU used in highly data-centric environments with an internal SBC embedded within a large FPGA. Applications can include a remote interface data concentrator, engine and power train control, and data monitoring as well as vehicle prognostics data collection and Condition Based Maintenance (CBM).

FPGA-based DCUs are ideal for these types of applications when coupled with a large variety of I/O interfaces and the large user-programmable FPGA for the application Operational Flight Program (OFP). This “SBC embedded in an FPGA” implementation provides a hardware and silicon, processor-specific technology isolation layer – essentially now processor agnostic and free from the processor component obsolescence that can cripple the long-term availability of a fielded subsystem.

Optimized for low SWaP, these small, lightweight DCUs and Remote Interface Units (RIUs) – with their self-contained “all-in-one” SBC – are highly useful in other environments: PC-based data concentrators and machine interface applications in manned and unmanned, ground, airborne, or space-based vehicles.

For military tracked and wheeled vehicle applications, SBC-based RIUs and DCUs can monitor key vehicle parameters and provide CBM functionality, thereby reducing the overhead costs of expensive, and most times unnecessary, periodic and preventative vehicle maintenance procedures.

When new, low-power, high-performance CMOS ARM and low-power Intel/AMD processors are paired with Power over Ethernet (PoE), these low-SWaP DCUs/RIUs can now be constructed and connected as flexible neural networks, meeting the system demands of tomorrow’s defense vehicles and platforms with less power harnessing, fewer connectors, and, therefore, higher reliability.

The overall weight reduction – combined with a slimmer profile and natural convection/radiation cooling in units that can dissipate from less than 1 W to no more than 20 W – makes these units ideal for a variety of industrial and military and aerospace environments.

Reliable computing for today’s critical environments

While the budgets of many military and avionics programs have come under fire, embedded computing manufacturers have stepped up to deliver integrated systems that help save both installation and maintenance time as well as costs. By combining higher-density components with low-power, cost-effective processing technologies, today’s SBCs can provide the enhanced functionality and performance requirements demanded by critical defense systems.

Doug Patterson is VP, Military & Aerospace Business Sector, for Aitech Defense Systems, Inc. Doug has more than 20 years of experience in marketing, business development, and product management, including technical and communications accomplishments in telecommunications and harsh environment electronics. He also holds three patents in advanced metered mailing systems and nonvolatile memory redundancy mapping in severe/harsh environments. Doug holds a BSEE from BEI/Sacred Heart University. He can be contacted at [email protected].

Aitech Defense Systems, Inc. 888-248-3248


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