Military Embedded Systems

Two new rad-hard ICs from Texas Instruments enable power savings


July 30, 2012

John McHale

Editorial Director

Military Embedded Systems

Two new rad-hard ICs from Texas Instruments enable power savings

DALLAS. Engineers at Texas Instruments have developed two new radiation-hardened ICS ? a floating point digital signal processor (DSP) and a 16M SRAM ? that produce power savings and improve FPGA efficiency.

Power-hungry FPGAs are handling much the floating point workload in satellite systems, says Anton Quiroz, Space Segment Manager at Texas Instruments in Dallas. The new TI DSP device – the 32/64-bit SMV320C6727B-SP – enables floating pint operations to be offloaded from the FPGA onto a DSP, creating power savings, he adds.

The new DSP (pictured) is an enhanced version of TI’s C67x CPU used on the C671x DSPs. It is compatible with the C67x CPU but offers improvements in code density, speed, and floating point performance per clock cycle. The CPU – which runs at 250 MHZ – has a possible maximum performance of 1,500 MFLOPS by executing as many as eight instructions – six that are floating point instructions – in parallel each cycle. The CPU natively supports 32-bit fixed point, 32 bit single precision floating point and 64-bit double precision floating point arithmetic.

Total ionizing dose resistance for the DSP is 110 Krad(Si) and it has SEL immunity to LET=85MeV. The DSP’s operating temperature range is -55 to 125 degrees Celsius. The device is available in a 256-pin ceramic QFP package and is expected to be released by the end of this year, Quiroz says.

TI’s new rad-hard SRAM – the monolithic asynchronous SMV512K32HFG – also provides size, weight, and power (SWaP) savings when used with FPGAs in a system due to its embedded error detection and correction (EDAC), Quiroz says. Some of rad-hard system architectures implement EDAC inside FPGAs, which takes up an extra bank of memory, he says.

The new TI SRAM has built-in EDAC to cut down on soft errors and a built-in scrub engine for autonomous correction – pin selectable as slave or master.

The SRAM makes use of radiation-hardening-by-design processes and substrate engineering to achieve a total ionizing dose of 300Krad (Si) and a SER6e9 rad (Si)/s and its latch-up immunity is >LET=110 MeV-cm2/mg (T=125 C).

TI discussed both devices at the Nuclear Space and Radiation Effects Conference (NSREC) earlier this month in Miami.

For more information, visit or email [email protected].


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