Curtiss-Wright
20130 Lakeview Center Plaza
Suite 200
Ashburn, Virginia 20147 [email protected]
https://www.curtisswrightds.com/
Suite 200
Ashburn, Virginia 20147 [email protected]
https://www.curtisswrightds.com/
Articles related to Curtiss-Wright
Radar/EW
FMC+ standard propels embedded design to new heights - Story
April 29, 2016
The updated FPGA Mezzanine Card (FMC+) specification has been developed and refined over the past year, promising unparalleled I/O density and backward compatibility. The VITA 57.4 working group has approved the spec and will present it for ANSI balloting in early 2016. The following article takes a closer look at this important new standard to see its implications for advanced embedded design.
Radar/EW
Rugged dual-channel 4 GSPS ADC/DAC in 3U form factor - Product
April 14, 2016
The VPX3-530 3U VPX Xilinx Virtex-7 FPGA ADC/DAC card from Curtiss-Wright is designed for defense applications such as signal intelligence (SIGINT), electronic countermeasures (ECM), and radar warning receivers (RWR). The rugged dual-channel 4 gigasamples per second (GSPS) ADC/DAC is packa...
Avionics
Safety-certifiable COTS modules speed and ease DO-254 safety certification - Story
April 14, 2016
The first step in the process is to determine the system's intended DAL level.
Radar/EW
Radar/EW
Long live VME! - Story
March 11, 2016
While the "V" in "VME" actually stands for "Versa" (as in "Versa Module Eurocard"), it could arguably also stand - especially in the defense and aerospace commercial off-the-shelf (COTS) market - for "venerable." For the decades prior to the advent of the VPX architecture in 2006, VME was unquestionably a de facto board standard for rugged open architecture systems. Today, there are thousands of VME boards installed in the field and untold millions of dollars invested in hardware and systems software currently used on those deployed systems.
Radar/EW
HPEC radar processing architecture meets goals of USAF next-gen radar study - News
March 10, 2016
ASHBURN, Va. The U.S. Air Force completed the Next Generation Radar (NGR) Processor Study. The results demonstrated that Curtiss-Wright?s proposed multiprocessor High Performance Embedded Computing (HPEC) Radar processing architecture has met the study?s target benchmarks.
