Military Embedded Systems

Exploiting direct RF FPGAs for electronic warfare


May 15, 2023

Rodger Hosking

Mercury Systems

As technologies evolve, government defense organizations steadily evolve electronic warfare (EW) solutions to counteract and then surpass capabilities of their adversaries by leapfrogging each other in an ongoing mission imperative to maintain dominance. Essential functions of EW systems are acquiring RF [radio frequency] signals of interest and then performing the required signal-processing tasks to deliver an effective response. This fosters new technologies and architectures that boost performance levels in both operations.

Several emerging FPGA [field-programmable gate array] architectures combine advanced RF [radio frequency] data converters and the latest processing engines within a single package. Using advanced silicon processes and packaging technologies, offerings include both monolithic designs and multi-chip modules. These new, highly integrated devices represent transformative technology for electronic warfare (EW) applications, yielding significant performance advantages over the traditional collection of discrete components that are typical of previous architectures.

Direct RF technology

One of the most challenging requirements of modern EW systems is to capture and generate high-frequency, wideband RF signals using high-speed data converters. These are typically connected to the antenna with analog frequency translation stages to convert between RF antenna signal frequencies and the lower IF [intermediate frequency] frequencies that data converters can digitize. These RF tuner stages require mixers, amplifiers, filters, oscillators, and numerous discrete analog components, all carefully packaged and shielded to maintain signal integrity, increasing cost, size, power, and complexity in any EW system.

The most straightforward approach to eliminate these cumbersome frequency translation stages is to boost the sampling rate and the maximum input signal frequency of monolithic data converters so they can handle RF signals directly with no translation. Performance levels of these so-called direct RF devices have advanced steadily, driven by the obvious benefits for commercial, industrial, and defense markets.

The vast size of 5G commercial wireless markets provides special incentives, because the large number of local, massive-MIMO [multiple input/multiple output] phased-array antennas each typically needs 64 transmit/receive elements to steer receive and transmit signal beam patterns. Antenna directionality is achieved by precisely shifting the relative phase of signals to each element, so each element requires its own signal-processing channel.

In such systems, eliminating the frequency translation stage from each channel not only saves SWaP [size, weight, and power] and cost, but also simplifies channel synchronization by removing analog RF components subject to component tolerances, aging, temperature drift, reliability, and maintenance issues. To address these problems, discrete monolithic direct RF ADCs and DACs [analog-to-digital converters/digital-to-analog converters] capable of directly digitizing RF signals at 1 GHz and above have appeared during the last decade.

In 2017, Xilinx introduced the acclaimed RFSoC [radio frequency aystem-on-chip) with eight 5 Gs/sec ADCs, eight 9.8 Gs/sec DACs, Zynq UltraScale+ FPGA fabric, multicore Arm processors, and dual 100 GbE interfaces, all within a single monolithic device, fully qualifying as a direct RF FPGA. The RFSoC data converters support RF signal frequencies up to 6 GHz and offer channel synchronous operation for phased arrays. Initially targeting the 5G wireless infrastructure market, the RFSoC was immediately embraced for defense applications including radar, countermeasures, EW, and communications.

Now, direct RF data converters offering sampling rates as high as 64 Gs/sec can directly digitize RF signal frequencies up to 38 GHz. Available as packaged BGA [ball-grid-array] devices or in chiplet form, these monolithic devices are extremely compatible with the new generation of FPGA processing architectures discussed next.

AMD Xilinx Versal ACAP FPGAs

AMD’s Versal ACAP [adaptive compute acceleration platform] devices based on its 7 nm silicon process consists of a series of six SoC architectures, each with specific blends of different processing engines and powerful peripherals, shown in Figure 1.

[Figure 1 | AMD Xilinx Versal ACAP FPGA includes a blend of adaptable FPGA, DSP, and AI [artificial intelligence] engines; direct RF converters; multicore Arm processors; network-on-chip; multirate Ethernet I/O; and system interfaces. Diagram courtesy Xilinx.]

The scalar engines include the dual core Arm Cortex-A72 application processor and the dual-core Arm Cortex-R5 real-time processor. Unlike most scalar processors that implement single instruction, single data structures, these Arm processors provide single instruction, multiple data (SIMD) operations. This boosts performance for many algorithms by processing more data for each sequentially executed instruction. Scalar processors target general applications, and the software is extremely portable across a wide range of platforms.

The adaptable engines utilize programmable logic FPGA fabric plus various types of memory, including block RAM, UltraRAM, and accelerator RAM. Configurable logic in FPGAs provides an ideal platform for real-time state machines, control logic, complex timing, Ethernet packet processing, and synchronization, all essential functions for many EW systems. These kinds of operations are often impossible for scalar processors, even those running a real-time operating system. High level design entry tools help development tasks for signal processing tasks, but less so for real-time logic and control functions.

Versal offers two types of intelligent engines: The DSP engines are specialized, highly efficient real-time signal-processing blocks that include fixed- and floating-point multipliers, accumulators, arithmetic units, data multiplexers, and barrel shifters for both scalar and vector data types. With over 14,000 DSP engines in the largest Versal devices, highly parallelized processing architectures can process real-time data streams from high-rate direct RF data converters. As a result, DSPs deliver the lowest latency of all processing classes. Because each new generation of FPGAs adds new types of fabric resources and enhanced DSP engines, configuration code for FPGAs tends to be quite family-specific, even for devices from the same vendor.

The other intelligent engines are AI [artificial intelligence] engines, each consisting of a 2D array of AI tiles, which come in two versions. The general AI engines are balanced to support both machine learning (ML) applications and advanced signal processing for beamforming, radar, FFTs, filters, video enhancement and image processing. The AI/ML engines are optimized for ML tasks including image and speech recognition, medical diagnosis, statistical arbitrage, and predictive analytics, and they also offer extended support for ML data types. For machine learning applications, they are eight times more efficient in the silicon area than DSP engines, reducing power by about 40%.

Onboard, flexible high-bandwidth memory (HBM) enables data transfer bandwidths up to 820 GB/sec, representing an 8-time increase in bandwidth compared to traditional DDR5. The Versal ACAP AI RF series, available soon, offers on-board direct RF ADCs and DACs, following the highly successful theme introduced by RFSoC.

To interconnect all of these numerous resources, ACAP includes an extremely wideband, configurable network-on-chip that offers a uniform interface and protocol to simplify system integration.

This heterogeneous mix of ACAP resources gives designers the freedom to assign compute power to the processing engine most suitable to the task at hand, and the ability to adaptively reassign resources as required. This flexibility of ACAP delivers as much as ten times the performance compared to dedicated processor types alone. Versal development tools target high-level design entry from frameworks, models, C-language, and RTL coding. Users can create a custom development environment to suit their project needs and programming preferences. Other Versal hardware/software platforms will evolve to help speed EW development tasks and support high complexity applications with extreme performance requirements.

AMD Xilinx ACAP direct RF FPGA products

Although the Versal ACAP AI IF series with the integrated direct RF data converters is not yet available, several product offerings combining the Versal ACAP with direct RF data converters have already been released. (Figure 2.)

[Figure 2 | Three AMD Versal ACAP direct RF solutions: 2a is the RFS1140RF system-in-package with single AI core and four-channel/64 Gs/sec ADC/DAC; 2b is the SCFE6931 SOSA aligned 6U OpenVPX card with two AI cores and optical I/O; 2c is the 5560 SOSA aligned 3U VPX card with Versal HBM FPGA and direct RF mezzanine.]

Intel Stratix 10 AX and Agilex 9 Direct RF FPGAs

Intel offers two families of Direct RF FPGAs, the Stratix 10 AX and the new Agilex 9 shown in Figure 3. These multi-chip modules take advantage of Intel’s chiplet fabrication capabilities to attach various combinations of chiplets to the main FPGA chip using EMIB and 2.5D packaging processes. The Intel Direct RF devices use the Jariet Electra-MA 64 Gsps 10-bit chiplet data converters for all three of the devices shown below. A fourth device listed in Figure 4 uses chiplets with 4 Gsps 14-bit ADCs and 12 Gsps 14-bit DACs.

[Figure 3 | Intel direct RF FPGA parts include Stratix10 AX devices using 14 nm silicon and Agilex 9 devices using 7 nm silicon. All use EMIB connections between the FPGa fabric and direct RF ADC/DAC chiplets.]

Figure 4 shows resources in four different Intel direct RF devices. Note that the AGRW027 and AGRM027 devices use the same FPGA chip, illustrating the advantage of using different types and combinations of chiplets for data converters and other peripherals to efficiently create new components.

[Figure 4 | A table shows Intel direct RF FPGA resource comparisons.]

Intel direct RF products

The industry’s first open architecture board using an Intel direct RF FPGA is the Mercury DRF3182 released in January 2023. (Figure 5.) The 3U OpenVPX card features the Stratix10 AX device. It enables direct RF digitization of four transceiver channels across a 2 GHz to 18 GHz frequency band to support numerous EW applications. Eight PCIe Gen3 x4 data plane ports deliver 64 GB/sec of data across the backplane to other cards.

[Figure 5 | The DRF3182 3U VPX direct RF Stratix10 FPGA has four 51.2 Gs/sec, 10-bit ADCs/DACs.]

As soon as the new Intel Agilex 9 devices become available, board vendors will be eager to incorporate them in open architecture embedded computing boards to speed adoption in deployed systems.

Direct RF FPGAs: the bottom line for EW

By eliminating the analog RF frequency translation stage of EW designs, direct RF not only reduces SWaP and cost, but it also boosts performance by reducing latency, minimizing analog phase and amplitude uncertainties, and simplifying channel synchronization. Direct RF data converters contain dedicated digital frequency translators (DDCs and DUCs) that can instantaneously tune across a very wide span of frequency to implement complex sweeping and hopping patterns, a critical advantage for many advanced countermeasure algorithms.

Traditional scanning receivers that sequentially tune across a span can easily miss such transients outside of the current scan window. Direct RF enables EW systems to “stare” across a wide frequency span to detect any transient spectral activity that might be of interest. Once a signal is detected, the direct RF wideband data converter stream can also be delivered to a DDC to zoom in on a narrow band of interest for signal exploitation.

Because EW systems must often track multiple targets simultaneously, they can take advantage of this flexible wideband/narrowband capability to operate multiple narrowband DDCs in parallel, each tuned to specific target frequencies located anywhere across the entire frequency span, and beamformed to specific target directions.

Following a similar strategy, a single direct RF front end can be shared by multiple, different EW applications by forwarding digital streams of specific bands of interest to specialized subsystems across fast network links.

One challenge imposed by direct RF data conversion is the extremely high data rate between the data converter and the signal processing resources. In the earlier discussion of product solutions, the best strategy is tightly coupling these sections using silicon or chiplet bonding within a single device to stream data across wide, local high-speed parallel buses. This also significantly reduces latency compared to slower JESD [standard for serial interfaces] serial links, now in widespread use for such connections.

The powerful heterogeneous processing resources of the latest classes of FPGAs enable a flexible choice of processing engines best suited to the wide range of required tasks including decoding, demodulation, decryption, signal classification, image processing, sensor fusion, target recognition, trajectory calculations, fire control, countermeasures, attack plan development, and many more. These processor task assignments are adaptable during a mission to optimize performance.

Flexible chiplet packaging affords much shorter development cycles of new FPGAs equipped with specific peripherals tailored to the required sensors needed for specific applications and platforms. With so many clear advantages and with devices and deployable products available now, emerging direct RF FPGA technologies will continue to revolutionize EW architectures

Rodger Hosking is vice president, Mercury Systems Mixed-Signal. Rodger has more than 30 years in the electronics industry and is one of the co-founders of Pentek; he has authored hundreds of articles about software radio and digital signal processing. Prior to Pentek, he served as engineering manager at Wavetek/Rockland, and he holds patents in frequency synthesis and spectrum-analysis techniques. He holds a BS degree in physics from Allegheny College in Pennsylvania and BSEE and MSEE degrees from Columbia University in New York.


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