Military Embedded Systems

Redefining sensor-edge processing

Story

February 05, 2021

By Tom Smelker

Today’s sensor-based systems often fail to perform at their full potential due to loss of fidelity in data processing or discarding data due to analog bandwidth limitations from the performance trade-offs required to meet size, weight, and power (SWaP) constraints. In addition, the most effective radar and electronic warfare (EW) response techniques demand extremely low latency as the signal transitions from analog RF to digital and back to RF. Heterogeneous 2.5D system-in-package (SiP) technology, a new trend in microelectronics that includes multiple die inside the same package, is proving to be an excellent match for sensor-edge processing requirements, as it integrates high-performance chiplets to support direct digitization of wideband RF signals.

 

Access to real-time information to make rapid decisions has become increasingly critical in our modern world. From checking commute times or hailing a rideshare to ensuring weather will not disrupt our plans and more, we rely heavily on mobile applications to tell us everything. Similarly, defense applications require processing vast amounts of sensor data in near-real-time to detect and mitigate threats while being implemented in hardware both small and rugged enough to function in a fighter jet or on a satellite.

Artificial intelligence (AI) for edge applications continues to drive global innovation, enhancing the requirement for powerful processing technologies to make quick decisions in high-risk scenarios. Traditionally, this processing is only available in a remote data center. However, unlike the commercial sector, defense applications do not always have the convenience of sending the data to a data center in the cloud for processing due to limited connections and security threats. Therefore, these systems must perform processing near the sensor, directly at the tactical edge.

To implement edge-processing solutions, embedded system designers traditionally have made tough compromises in the trade-off between processing power and physical size. One common approach to address these challenges is a board-level solution, which integrates a variety of packaged semiconductor devices while dedicating significant space to device interconnections. Over time, these boards have become larger as more functionality has been required. Additionally, as the distance between devices increases, these sensor-based systems are losing performance, speed, and fidelity in data processing due to analog bandwidth limitations.

Another common solution is a custom-designed application-specific integrated circuit (ASIC). While this approach yields maximum size, weight, and power (SWaP) optimization, it lacks the analog bandwidth required in today’s rapidly evolving defense environments and is extremely expensive. Plus, since an ASIC cannot be modified after its initial design, each variant has a five- to seven-year development cycle, making it an ineffective solution.

Sensor edge processing challenges

Delivering powerful AI-grade processing for suitable operation in defense applications at the tactical edge requires a new approach. The most effective radar and electronic warfare (EW) response techniques demand extremely low latency as the signal transitions from analog RF to digital and back to RF.

Implementing this requires that transceivers, directly connected to an antenna, capture broadband data in analog form and move it to analog-to-digital converters (ADCs), where it is transformed into a digital bitstream. From there, it is processed by either a field-programmable gate array (FPGA) or a general-purpose processor before being moved back through digital-to-analog converters (DACs), to the transceiver, and then the antenna. As the complexity of these signals increases, the demand on the RF and digital processing systems increases as well.

Radar spoofing is one critical example of this technology, where embedded components as part of an electronic attack (EA) system detect, alter, and then replay radar pulses to create false targets. To successfully deceive the latest radar systems, the latency must be so low that the adversary’s radar system cannot perceive a time lag in the replayed pulse (Figure 1). Additionally, in order to support cognitive capabilities, the EA system must be capable of performing advanced AI-level processing directly adjacent to the sensor aperture.

[Figure 1 | Low-latency edge processing deceiving the targeting radar from enemy attack. Image courtesy Mercury Systems.]

Hypersonic weapons, moving at speeds of Mach 5 or greater, are the next wave of threats. To counter them, defense systems require powerful levels of low-latency AI processing on a wide range of platforms. In our current environment, the bandwidth from these sensors would overwhelm the RF front ends and system-level interconnects, forcing substantial data reduction and impossible transmission times before processing.

Given all the drawbacks to current solutions, it is not surprising that system designers are looking for a better approach to meet the demands of sensor-edge computing. They need high-performance, SWaP-optimized, chip-scale implementations and tightly integrated analog and digital functions in a highly customizable and low-cost solution for specific application requirements.

A new approach to semiconductor design

Heterogeneous 2.5D system-in-package (SiP) technology can be a match for sensor-edge processing requirements. In this technology, high-performance chiplets – semiconductor die and chipscale component building blocks – support direct digitization and low-latency AI processing of wideband RF signals. For example, a SiP could include a set of chiplets for RF capture and transmission, ADC/DAC conversion, digital I/O, and FPGA-based digital signal processing. With each of these chiplets performing a specific function, the SiP can be easily optimized for multiple applications.

As mission-critical applications at the tactical edge drive the demand for low-latency processing in ever-shrinking form factors, high-performance SiP devices accelerate edge computing deployment. These high-performance signal-processing solutions are small enough to fit in the palm of a hand while also rugged enough to withstand shock, vibration, and temperature extremes present in defense environments. In addition, the commercial semiconductor industry is regularly bringing new chiplets to market, and a SiP fosters the ability to replace chiplets instead of modifying external components, thus shortening development time. Working at chipscale, the new 2.5D capability enables designers the ability to combine multiple complex semiconductor dies into a single component while maintaining trust and security.

Implementing 2.5D SiP solutions

To develop an application-specific SiP solution, chiplets are mounted onto a custom piece of silicon called the interposer, which includes high-density, through-silicon via (TSV) technology for routing signals between the chiplets and out of the package. This design reduces both latency and physical size. Small-size, low-weight, and minimal-power 2.5D SiP designs can replicate the functionality of a 6U OpenVPX board in a form factor smaller than a business card. (Figure 2.)

[Figure 2 | Demonstration of space-saving capability of SiP technology.]

With the interposer, a variety of high-frequency signals are routed between chiplets in a small space, minimizing crosstalk and other threats to signal integrity – but as the electrical behavior of these signal connections over a broad range is difficult to model, SiP manufacturing requires specialized expertise and fabrication equipment. However, because it consists of only interconnects and no logic, an interposer can be laid out and fabricated in up to half the time it would take for a monolithic ASIC. Additionally, the same interposer design can be easily customized to support multiple applications and programs.

With faster time to market and lower total cost, 2.5D SiP is preferred for many commercial applications. Mixed-signal designs for radar and EW map well into combinations of chiplets, since they can flexibly incorporate a variety of CPUs, GPUs, and FPGAs to a specific application and then combine them with transceivers and ADC/DAC components that match the targeted RF band. This level of customization enables advancements in custom silicon to be quickly and easily applied, providing added value without added expense or program disruption.

A new sensor-edge processing project can design, fabricate, test, and deploy a customized, 2.5D SiP solution in two or three years, compared to the five- or seven-year time frame of a custom ASIC. Such an approach can also include patented chiplets, giving potential users a straightforward way to build differentiating capabilities into a solution offering.

Enabling new solutions

SiP integration can be used to implement new types of solutions that are not possible with traditional RF and digital processing technology. For example, most existing active electronically scanned array (AESA) radar systems are optimized for specific applications, such as surveillance radar or electronic warfare. This results in a single platform, such as a naval vessel, requiring multiple radar arrays.

By using broadband 2.5D SiP technology, digitization and signal-processing functions can be integrated into a single AESA that can perform multiple functions, such as identifying and using a portion of an array to mitigate a missile threat, while also targeting a weapon on a different part of the array – all while continuing to scan for new threats. (Figure 3.) Since these different applications operate over different frequency ranges, achieving this flexibility requires broadband RF and powerful digital processing at each antenna array element, which can be supported by 2.5D SiP integration.

[Figure 3 | Example of SWaP-constrained airborne AESA radar system. U.S. Air Force photo.]

As part of the leadership in the SOSA [Sensor Open Systems Architecture] community, Mercury’s 2.5D SiP enables SOSA-aligned solutions at the module level. At the chip level Mercury is leveraging open systems architecture for faster adoption of advanced chiplets for defense applications.

Tom Smelker is vice president and general manager of custom microelectronic solutions at Mercury Systems Custom Microelectronic Solutions in Phoenix, Arizona. He is responsible for the management of multidisciplined teams developing advanced solutions in semiconductor technologies at the system and subsystem levels for applications in embedded defense computing and systems security technologies. Prior to joining Mercury, Smelker spent nearly 20 years as a Senior Engineering Fellow and systems design program manager at Raytheon Missile Systems. Smelker began his career as an Undergraduate and Graduate Fellow at the U.S. Army Research Laboratory. He has a master’s degree in mechanical engineering (non-linear controls) from New Mexico State University and a bachelor’s degree in mechanical engineering with a minor in mathematics, also from New Mexico State University.

Mercury Systems    https://www.mrcy.com/

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