New SPARC-based microprocessors announced by Aeroflex Colorado Springs at NSREC
NewsJuly 09, 2013
SAN FRANCISCO. Engineers at Aeroflex Colorado Springs released new microprocessors this week at the Nuclear Space and Radiation Effects Conference (NSREC) in San Francisco. The products – UT699E and the UT700 – have more performance on a 130-nanometer CMOS process.
“The UT699E next-generation microprocessor is an enhanced version of our UT699,” says Tony Jordan, Director of Standard Products at Aeroflex Colorado Springs. “We basically migrated the product from .25 micron CMOS to 130 nm CMOS, resulting in a faster microprocessor with targeted speeds of 133 MHz that is also lower power.”
The UT699E features a seven stage pipelined monolithic, high-performance, fault- tolerant SPARC V8/LEON 3FT Processor, according to the Aeroflex data sheet. The device’s L1 cache increased to 16kB for instruction and data caches and performance has increased to 1.2 DMIPS/MHz. the RMAP protocol is supported for all of the device’s four SpaceWire ports. Additional enhancements include cache snooping. The device has a 32-bit master/ target PCI interface, which includes a 16-bit user I/O interface for off-chip peripherals. A compliant 2.0 AMBA bus interface integrates the on-chip LEON 3FT, SpaceWire, Ethernet, memory controller, cPCI, CAN bus, and programmable interrupt peripherals. The UT699E also is SPARC V8 compliant. Aeroflex provides full software development suite that includes a C/C++ cross-compiler system based on GCC and the Newlib embedded C-library. Software developed for the UT699 also will be 100 percent compatible with the UT699E.
“We also are announcing the UT700, which is a derivative of the UT699e that has a more powerful EDAC scheme” as well as a 1553 port to support the bus controller remote terminal function, Jordan says. “We have many customers who still require legacy 1553 capability.”
The UT700 has a seven stage pipelined monolithic, high- performance, fault-tolerant SPARC V8/LEON 3FT
Processor, according to an Aeroflex datasheet. Its L1 cache has 16kB for instruction and data caches. A Reed Solomon EDAC provides fault-tolerant protection for the SDRAM. Integer performance is at 1.2 DMIPS/MHz. Like the UT699e the RMAP protocol is supported for all four SpaceWire ports. The UT700 provides a 32-bit master/target PCI interface, including a 16-bit user I/O interface for off-chip peripherals. A compliant 2.0 AMBA bus interface integrates the on-chip LEON 3FT, SpaceWire, Ethernet, memory controller, cPCI, CAN bus, MIL-STD-1553, SPI and programmable interrupt peripherals.
It too is SPARC V8 compliant.
While the UT699 and UT699e are pin to pin compatible, the 700 is not, he adds. “We are adding additional IO and improving the EDAC scheme so it has a slightly different pin out but is offered in similar packages to the other devices. With these new products we are upgrading processing capability and keeping the same footprint.”
For more information, visit www.aeroflex.com/radhard.
