Radiation-tolerant FPGAs solve the satellite signal processing bottleneckStory
June 12, 2015
Dramatic increases in sensor resolution in remote-sensing space payloads are causing a processing bottleneck, as downlink bandwidth is not keeping pace. Operators require onboard processing so that satellites send processed information, not just raw data. It is a growing challenge for the roughly 100 remote sensing satellites launched each year, each carrying as many as eight payload instruments. Flash-based field-programmable gate array (FPGA) technology is now being applied to the problem, combining high-speed signal processing with special built-in radiation mitigation techniques to keep systems operational in harsh radiation environments.
Military satellite operators have an insatiable thirst for data, and are therefore specifying remote-sensing satellites with ever-increasing sensor capabilities. In addition to increased resolution, imaging sensors are required to cover broader spectra, infrared detectors are required to have higher sensitivity and finer spectral channelization, and synthetic aperture radar systems are required to perform additional processing steps such as polarimetry or interferometry in order to extract additional useful information from the radar data. While sensor developers have been able to meet the need with increasingly sophisticated and capable sensors, the available bandwidth to transmit data back to Earth has not been increasing as quickly. This information glut creates a growing requirement to perform signal processing on board the satellite, so that downlink bandwidth is used efficiently. Figure 1 shows the architecture of a generic remote sensing satellite payload instrument.
Figure 1: Generic remote sensing payload architecture.
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Historically, this data-overload problem has been solved by using radiation-hardened application-specific integrated circuits (ASICs), which have sufficient density and performance to accomplish the high-throughput signal processing required. ASICs have some significant disadvantages, however: For one thing, ASIC developers are required to pay a large nonrecurring engineering charge (NRE), which covers tooling costs for the ASIC (for example, making masks for the 40-plus diffusion, deposition, and etching steps involved in making a modern integrated circuit). The NRE also compensates the ASIC vendor for first silicon wafers, and also for the time and effort expended by the application team in supporting the developer through the design, timing closure, and verification process. NRE costs can run as high as several million dollars; for satellite designs, these costs are amortized over a small number of units. The fabrication cycle time on a radiation-hardened ASIC is long, and it can be as much as six months before a design team gets to see if their ASIC design actually works as intended. If part of the ASIC needs to be redesigned, then additional NRE must be paid, and delays to the project will be incurred as another cycle through fabrication is necessary. This presents a very high degree of risk to satellite program managers. Many military satellite programs charge subcontractors penalties for late delivery of systems that can run into thousands of dollars for each day of delay. More significantly, delays to the launch of a military satellite can create a national-security risk, as it may mean that a key component of a reconnaissance or missile-detection mission is not in place in time.
An alternative to using an ASIC is to use large high-performance FPGAs. The largest FPGAs with packaging and testing suitable for space applications have historically been static random-access memory (SRAM)-based. While these FPGAs bring some benefits of rapid prototyping and validation due to their reprogrammability, which mitigates the risks of using an ASIC, they introduce some other disadvantages. SRAM-based FPGAs use SRAM cells to switch pass transistors on or off. These pass transistors connect or disconnect routing tracks and configure the function of the programmable logic resources in the FPGA. Any radiation upsets in the SRAM cells can cause the FPGA’s design configuration to change, causing a malfunction in the system. Designers working with SRAM FPGAs need to be aware of the risks of malfunctions caused by radiation upsets in SRAM configuration cells, and must be prepared to take steps to mitigate their design. The latest SRAM FPGAs intended for radiation environments include modifications that reduce, but do not eliminate, such errors. Designers need to take further mitigation steps which involve reading and correcting the FPGA configuration memory with a radiation-hard scrubber circuit, which increases power consumption, board space, and system mass. This technique doesn’t prevent errors, it only corrects them after they have occurred. In this situation, a military mission may be compromised as the SRAM FPGA is not functioning correctly during the period between occurrence and detection of the configuration error.
Clearly, an alternative approach to digital logic integration in space-based signal processing applications is required, which mitigates the risk of the ASIC and SRAM FPGA approaches. Flash-based FPGAs offers a new angle to solving this signal processing congestion problem. Today’s flash-based FPGAs combine an architecture optimized for signal processing applications with a 65 nm flash process, which is intrinsically hard against loss of configuration due to radiation in space.
Many architectural features are needed to enable high performance in signal processing applications. An abundance of flip-flops in the programmable logic fabric is a prerequisite, as high-performance designs often make heavy use of data pipelining in order to maximize the operating clock frequency. High density and high performance of the programmable fabric is necessary but insufficient. To be successful in high-speed signal processing applications, FPGAs must also have ample hardwired multiply-accumulate blocks, copious amounts of embedded SRAM memory, and high-speed I/Os, both serial and parallel, in order to get signals on-chip and off-chip quickly.
Modern geosynchronous satellites are required to remain functional for up to 20 years after launch. For deployment in space, FPGAs must be able to survive the radiation environment for the duration of the satellite life without any destructive or catastrophic failures, such as single-event latch-up or configuration upsets. The flash cells that control the configuration of 65 nm flash FPGAs are intrinsically immune to upsets caused by subatomic particle radiation in space. This has been demonstrated through several rounds of radiation testing using high-energy heavy ions in tests. In these tests, FPGAs are bombarded by energetic heavy ions at rates literally millions of times greater than they will be subjected to in the space environment, allowing radiation scientists to gather enough data to simulate a satellite lifetime in a few hours. In this testing it has also been shown that “radiation-hardening-by-design” techniques in combination with the 65 nm process used to build these FPGAs have eliminated the possibility of single-event latch-up in space applications.
For data paths carrying mission-critical or flight-critical data, flip-flops require protection against radiation single-event upsets, and combinatorial logic may require single-event transient mitigation. Protection of flip-flops against upsets caused by subatomic particle radiation is usually accomplished by using triple module redundancy within each flip-flop in conjunction with a self-correction scheme, which corrects any radiation upsets asynchronously and prevents upsets from propagating outside of the logic cell.
Single-event transients have become significantly more important in modern submicron integrated circuits. Firstly, as manufacturing processes shrink to finer geometries, the energy a subatomic particle needs to transfer in order to cause a glitch in combinatorial logic decreases. Compounding this situation, as clock frequencies increase, the probability of a glitch in combinatorial logic occurring within the sample-and-hold time of flip-flop increases. As a result, single-event transients have become a significant concern for designers of electronic systems that are intended to be deployed in environments with large amounts of particle radiation, such as space. The length of the delay (ΔT) will determine the maximum duration of transient which the circuit can filter. The ΔT must be chosen carefully by the FPGA vendor so that it is effective at screening out the majority of radiation-induced transients, while at the same time having as little impact on the performance of the FPGA as possible.
In FPGAs offering embedded single-event transient mitigation circuits such as this, the value of ΔT is derived after a series of radiation experiments on test chips representative of the final design of the FPGA logic element. Figure 2 shows a scheme for embedding single-event transient mitigation into an FPGA logic element.
Figure 2: An embedded single-event transient filter.
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SRAM memory blocks can be protected against radiation upsets by built-in error detection and correction (EDAC) encoding, which will correct any single-bit error, and detect any double-bit error. It is particularly helpful if the memory EDAC decoder circuit raises a flag if it corrects a single-bit error, and raises another flag if an uncorrectable double-bit error is detected. The probability of encountering a double-bit error can be dramatically reduced by the use of physical interleaving, so that logically-adjacent memory bits are physically dispersed in the FPGA. The probability of a single subatomic particle causing two upsets in the same logical word is made extremely low by the physical separation between logically adjacent bits. Figure 3 shows the use of physical separation to protect memory structures against multiple bit upsets.
Figure 3: Physical separation protects SRAM blocks against multiple bit upsets.
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Microsemi’s latest family of radiation-tolerant flash-based FPGAs, the RTG4 family, features a high-performance architecture tuned for signal processing applications. Benchmark results on RTG4 indicate a signal processing performance advantage of up to 40 percent against SRAM-based radiation tolerant FPGAs on a variety of signal processing designs. The 65 nm flash process used in RTG4 is intrinsically immune to configuration upsets. These FPGAs are designed to eliminate single-event latch-ups due to radiation in space, and feature radiation protection of data in flip-flops and combinatorial logic elements, embedded SRAM cells, and multiply/accumulate blocks. Radiation testing has demonstrated that the radiation-hardening-by-design techniques are successful in providing sufficient protection for the vast majority of space missions, including 20-year geosynchronous Earth-orbiting missions.
Satellites performing remote-sensing missions face a significant signal processing bottleneck, as advances in downlink bandwidth are not keeping pace with developments in sensor resolution. As a result, satellites are required to perform more on-board processing, so that useful information – not just raw data – is transmitted to Earth. ASICs and SRAM FPGAs have significant disadvantages when used in these applications. However, modern radiation-tolerant flash-based FPGAs provide a compelling alternative, reducing program cost and schedule risk while at the same time providing the necessary mitigation of radiation effects to assure reliable operation and mission success.
Ken O’Neill is Director of Marketing, Space, and Aviation, with Microsemi’s SoC Products Group. He has supported FPGA applications in space, aviation, and other high-reliability markets for 25 years. O’Neill originally joined Microsemi in June 1990 as a Product Marketing Engineer and has held several marketing and field applications engineering positions. Before joining Microsemi, O’Neill served as a Design Engineer with Hewlett-Packard’s Computer Peripherals Group. Prior to that, he was a Design Engineer with Racal-Comsec Ltd. O’Neill holds a bachelor’s degree in electronics engineering from the University of Reading, England. Readers may reach Ken at [email protected]
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