Avionics bus interface revolutionStory
July 08, 2008
Avionics buses are traditionally slow to evolve, partly because requirements change so slowly and partly because of the costs of development, certification, and sustainment. It is with the development of new airplanes that the demand for new bus architectures evolves. This can be seen in the adoption of Fibre Channel for JSF and ARINC 664, also known as AFDX for new Boeing and Airbus airplane types.
Avionics buses are traditionally slow to evolve, partly because requirements change so slowly and partly because of the costs of development, certification, and sustainment. It is with the development of new airplanes that the demand for new bus architectures evolves. This can be seen in the adoption of Fibre Channel for JSF and ARINC 664, also known as AFDX for new Boeing and Airbus airplane types. Some buses, although ideally suited technically such as Time Triggered Protocol (TTP), have been sluggish to be adopted and might only find use in niche applications. However, although the rate of change might be slow, the nature of the market still leaves room for much innovation in packaging, soft cores, and test equipment by embedded computing vendors.
Avionics architectures typically separate the flight safety-critical elements such as primary flight control, cockpit, landing gear, and so on from less critical elements such as cabin environment, entertainment, and, in the case of military aircraft, the mission systems. This separation offers less onerous initial certification and allows incremental addition, as is often required for regulatory reasons, without the need for complete recertification. Significant savings in weight and power could be made with an integrated systems approach, using centralized computing supporting individual applications running in secure partitions with critical and non-critical data sharing the same bus. The most widely adopted of these is ARINC 664.
Other safety-critical bus technologies provide the same capability. For example, TTP is designed to provide time domain separation of groups of participants (such as nodes) on a bus. TTP can support a single fixed group or multiple groups; each participant within each group and each group are allowed time slots on the bus that are scheduled to ensure that every participant always has time to complete its data transfers. TTP can also detect whether scheduled participants are present and working correctly; it can detect transmission errors and tolerates faulty nodes. MIL-STD-1553B is similarly deterministic in its scheduling of bus traffic, but TTP is much more flexible and capable. However, MIL-STD-1553B is firmly entrenched in military avionics and mission systems. Because of this widespread use, it still remains the medium of choice for many upgrade and improvement programs.
Typical COTS-based military avionics subsystems use modules such as VMEbus, CompactPCI, or VPX configured in an enclosure. It is a key requirement to add MIL-STD-1553B interfaces in a modular form to these subsystems, and the PMC form factor is the preferred choice. Other solutions include small mezzanines on SBCs or entire dedicated modules, adding eight or more dual-redundant interfaces into a single subsystem. But small-scale embedded subsystems can now be implemented as a System-on-Chip (SoC) using the latest generations of FPGAs. This creates opportunities for COTS vendors to offer 1553 IP cores for single or multiple remote terminals, bus controller, and bus monitor functions, extending the COTS value proposition well beyond the traditional board supplier.
Avionics interfaces on ExpressCard
With the continued development of new applications for avionics interfaces, bus analyzers play an important role in the testing and verification process. Similar to many market sectors, the laptop computer has become the ubiquitous test vehicle, easily supporting the four basic analyzer functions of display, logging and analysis, simulation, and playback when hooked up to a test rig or aircraft system. The laptop's PCMCIA slot has, until recently, been used to connect to the system under test. However, PCMCIA is rapidly being displaced by the new ExpressCard standard. This replaces the parallel interface of PCMCIA with PCI Express, offering significant improvements in performance and bandwidth plus compatibility with many other forms of embedded computing technology.
Despite its small size, an ExpressCard can support a dual-redundant AFDX port, logging all bus traffic, complete with 64-bit time tagging and IRIG-B for synchronization with external time sources. The RAF-EC AFDX ExpressCard module (Figure 1) is designed for use in avionics bus analyzers, along with its sibling ExpressCard products for MIL-STD-1553B and ARINC 429. The RAF-EC and MIL-STD-1553B soft cores are produced by GE Fanuc Intelligent Platforms.
While it appears that avionics buses are being left behind by the pace of technological change, there are sound economic and safety reasons why avionics architectures cannot change so rapidly. Appropriate new technologies such as TTP, developed for the automotive sector, are slow to migrate from their native markets even with proven certification to RTCA requirements. However, the pace of technological change will ensure that competitive innovation will continue to refine and improve the choices of avionics bus products available from the COTS market.
To learn more, e-mail Duncan Young at [email protected].