MIL-STD-1553 IP cores challenge traditional IC implementationStory
March 11, 2014
Forty years since its release, MIL-STD-1553 is evolving from traditional Integrated Circuits (ICs) to Intellectual Property (IP) cores integrated with Field Programmable Gate Arrays (FPGAs). The advantages of IP core implementation include cost reduction, the ability to upgrade and adapt a design over time, a smaller size footprint, and improved sourcing. Designers choosing IP cores must consider validation testing, code size, FPGA support, and compatibility with legacy software.
MIL-STD-1553, introduced in 1973, is a dual-redundant serial bus widely used in avionics and space applications. Originally used in the F-16, 1553 connects a Bus Controller (BC) to as many as 31 Remote Terminal (RT) devices at a 1 Mbps data rate.
Those early 1553 designs were quite complicated: BC and RT units connected to the processor’s bus using transformers, while transceivers converted the analog signals to and from digital signals. A digital controller converted the digital signals to and from Manchester code, managing the entire process of receiving and transmitting data in accordance with the 1553 specifications.
Approximately 15 years later, the first gate-array Application-Specific Integrated Circuits (ASICs) were produced, offering a single chip that could handle the entire digital portion of the 1553 board. About the same time, the analog transceiver was condensed from discrete devices into a single module. Next, several companies created hybrid circuits integrating the required digital and analog parts into a single IC. Once introduced, these single mixed-signal ICs dominated the market as the solution for 1553 communications.
Fast-forward to today: The latest emerging technology in MIL-STD-1553 is the IP core. The 1553 IP cores integrate with other user logic into an FPGA, offering designers numerous advantages over traditional 1553 ICs.
Benefits of IP cores
Embedding 1553 functionality into an FPGA with other design requirements yields significant cost savings. In addition to the cost of the FPGA, the incremental price per 1553 node is only the cost of the analog transceiver and the IP core use-license. Since there are many suppliers for analog transceivers, pricing is competitive, and this architecture can deliver more than 50 percent cost reduction in 1553 node price for moderate quantities.
Ability to upgrade
Once a 1553 IC is soldered to a board the device’s functionality cannot be changed. Since FPGAs can be reprogrammed, the 1553 functionality can be enhanced, modified, or even replaced by a new IP core if required. This architecture also allows for various bus device configurations – such as one, two, or more channels, or even different interface types such as WB-194 or H009 – without any change in FPGA technology or PCB hardware. FPGAs make upgrades simple as they can be reprogrammed in the field – even via the 1553 bus in some cases.
Less board space
The IP core typically consumes 2 to 15 percent of a common FPGA, often enabling it to be integrated into an FPGA already handling other functionality in a particular design. In this case, only an additional small analog receiver is required to implement 1553, reducing the size required for the PCB. Figure 1 (on page 32) shows a PCI Mezzanine Card (PMC) that packs eight 1553 channels into a 74 mm by 143 mm footprint.
Easy evaluation before committing
Free IP core evaluations can be quickly supplied by IP vendors upon request and all functionality can be evaluated and simulated before a single trace is routed for the PCB. These samples may include a limited version of the core, allowing 95 percent of the functions contained in the full core. The designer can check simulations, integrate the limited IP core, and test the behavior in the lab, which will reduce risks, costs, and design time.
IP cores are not FPGA specific and the core can be moved to a different FPGA part if the first FPGA part becomes obsolete. This compatibility enables users to easily update their board and FPGA device while maintaining the proven functionality.
Eliminates single source
Each 1553 IC has a unique interface and functionality, making it nearly impossible to easily change vendors for the parts since it would require a hardware and software redesign. Having a sole source raises price, availability, and obsolescence concerns. An IP core implementation eliminates these problems. Once the IP core is licensed to a customer, the supply chain is simplified. The customer integrates the IP core in the form of EDIF netlist into the FPGA and procures the FPGA from a variety of distribution sources themselves, eliminating the dependence on the 1553 IC vendor.
Figure 1: MIL-STD-1553 eight-channel PMC module.
(Click graphic to zoom by 1.9x)
Important considerations in choosing IP cores
MIL-STD-1553 IP cores are available from several companies and, as you might expect, performance and quality can vary. To choose the best solution for their particular application, designers should compare key attributes of 1553 IP cores.
The first would be 1553 validation testing. Full 1553 validation testing is required to certify proper IP core compliance to MIL-STD-1553 electrical and software requirements. Choosing an IP core that has been approved through third-party testing will prevent surprises and delays later in the project. Another piece to consider is that of small code size. As discussed before, one of the advantages of IP cores over ICs is the fact that IP cores can reside within an FPGA that performs other functions as well. To allow room for this additional functionality while keeping FPGA cost reasonable, the IP core should require minimum FPGA resources.
Support for a range of FPGA vendors and families
Another consideration for designers is that IP cores should fit any FPGA vendor and family. FPGA families range from general purpose to devices with specific characteristics such as radiation resistance, low power, non-volatile, and high memory volume. Designers can select the appropriate FPGA for their application and IP vendors should be able to supply the appropriate netlists for the parts. The VHDL source code from which the netlist is produced should be vendor independent in code style to support all FPGA families.
Multiple clock domains may cause overhead in FPGA design, or in some cases bad data read/write cycles. It is important, therefore, that the IP core support a clock frequency that is already available on the target board, such as PCI Express (125 MHz) or PCI (33/66 MHz).
One last consideration is compatibility with legacy software. Software integration is a critical consideration for applications migrating from an IC-based design to an IP core. In many cases, designers will not want to make changes to their existing, working software environment. IP cores should be software compatible with legacy 1553 ICs, allowing the designer to replace an existing 1553 IC with an FPGA-based IP core with minimal risk.
IP cores specifically for military, avionics
IP cores offer many advantages over traditional 1553 ICs including lower cost, reduced size, easy ability to update, improved availability, and lifecycle control. Combining the benefits of FPGAs and IP cores provides a small-size, robust, reliable, and future-proof solution for MIL-STD-1553 interface, perfect for custom board implementations.
Sealevel Systems, Inc. has partnered with Sital Technology to supply MIL-STD-1553 IP core products engineered for military, aerospace, and avionics applications. Users can choose between various available configurations and interfaces. From the small 1553 Front-End, designed for simple applications where no CPU is controlling the system, to the most complex implementations, where a local bus is used by the CPU or where PCIe or PCI bus is used.
All IP cores available from Sealevel work with any FPGA, clock frequency, and 1553 transceiver. Each IP core is third-party tested and offers software compatibility with existing ICs.
Marc Foster, Director of Strategic and Government Sales at Sealevel Systems, Inc., has more than 12 years of experience designing solutions for military applications. Marc graduated from Clemson University in 1997. Before joining Sealevel’s team in 2001, Marc worked in business development for Synnex Corporation where he developed solutions for communications platforms. Readers may reach him at [email protected]
Sealevel Systems 864-843-4343 www.sealevel.com