Multicore packet processors boost system and I/O performanceStory
July 14, 2010
Multicore packet processors can be successfully adopted from other markets because they meet the military's sustainable, long-term commitment needs in addition to being high performance.
Multicore packet processor devices have found widespread use in commercial information processing and networking applications such as file servers, secure gateways, protocol offload engines, and so on. They are equally applicable to wider DoD and international defense infrastructure projects, but also offer great scope for innovation within deeply embedded military systems. Packet processors with typically 8 to 16 industry standard, general-purpose cores based on either Power Architecture or MIPS64 (Cavium Networks) can run multiple independent or cooperative tasks on a single device. While many network-oriented applications are available off-the-shelf, the wealth of tools and environments for these well established processing cores facilitates additional task development and integration for each new project requirement.
Typical file server application
A typical use for packet processors is to improve an existing installation’s service by, for example, replacing an off-the-shelf file server’s NIC card. Such servers are often limited by I/O bandwidth and the computing power needed to service the many users and network connections. The processing functions for protocol stacks, payload encryption (for IPv6), and network services and security can all be offloaded to a packet processor to restore the server host processor’s performance and responsiveness.
SoCs increase computing density
Embedded military applications in small platforms such as land vehicles, helicopters, combat aircraft, and Unmanned Aerial Vehicles (UAVs) are rarely as conveniently segmented as the commercial file server example. In addition to network performance and security issues, these systems are required to resolve a complex set of real-time problems such as sensor and I/O processing, sensor fusion, target tracking, weapons direction, and platform management while consuming the least possible space, weight, and power. To achieve the next levels of processing density, system designers are exploring new territory by using one or a number of the many recent types of System-on-Chip (SoC) multicore application accelerators. For example, the latest generation of high-performance Graphics Processor Units (GPUs) has large arrays of processing cores optimized for repetitive, multithreaded video and image processing. Similar in concept but intended for quite different tasks, packet processors can be used to offload tasks such as I/O interfacing, complex decision-making algorithm execution, system security, or network management from a subsystem’s host processor.
As a result, packet processing devices primarily designed for high-volume, commercial applications are receiving increasing attention from embedded designers. A device like Cavium Network’s OCTEON will typically incorporate 8 to 16 independent MIPS64 processing cores, running at close to GHz clock rates with options for integrated protocol, compression, and encryption engines, plus support for file server and network security applications. The I/O is a mix of 1 GHz and 10 GHz Ethernet ports plus PCI Express ports. Both of these interface types are commonly used by sensor equipment such as radar, sonar, and Electro-Optical (EO) to stream digital sensor video. Also like other SoC-based technologies, packet processors require a host PC-based processor. A Linux SDK package, including ported OS and communications with the host, provides a platform for developing tasks for individual cores as well as the integration of off-the-shelf communication and network packages to provide the complete system alternative.
Packet processors provide network security
Weapons platforms usually comprise a number of sensor and processing subsystems that communicate intensively with each other and externally with other platforms and networks. A packet processor can also be used as a secure gateway for the platform’s external communications to provide the perimeter defense needed to protect the onboard embedded subsystems. In addition to the common IP-related routing and Denial of Service (DoS) attacks, a packet processor has the performance to inspect the header and payload of packets at wire speed to detect and prevent malicious code, viruses, or deliberate data obfuscation. This also applies to collecting statistical data on potentially abnormal network traffic patterns.
For embedded systems, the OCTEON packet processor is available from GE Intelligent Platforms in open architecture formats such as PCI Express or AdvancedMC. The AdvancedMC format offers compatibility with the increasingly popular MicroTCA equipment practice for military applications. Meanwhile, the PCI Express format, depicted in Figure 1, is intended for use in benign applications or the development laboratory.
Figure 1: The PCI Express format OCTEON-based packet processor
(Click graphic to zoom by 1.9x)
Meeting military needs
The packet processor is an example of how technology can be successfully adopted from other markets and used in innovative ways for deployment in military embedded subsystems. However, because of the nature of military development projects, the technology must be sustainable, with long-term commitments to roadmaps and support before it can be considered. Packet processors meet these criteria and have the performance and capability to step beyond their communications roots and offload many other critical tasks in embedded environments.
To learn more, e-mail Duncan at [email protected]