FPGAs gearing up to dominate DSP applicationsStory
October 30, 2005
AltiVec PowerPCs have enjoyed dominance in high-end military signal processing applications such as Software-Defined Radio (SDR) and video/image compression. But FPGAs, with their inherent parallelism and reprogrammability, are fast becoming prevalent ...
AltiVec PowerPCs have enjoyed dominance in high-end military signal processing applications such as Software-Defined Radio (SDR) and video/image compression. But FPGAs, with their inherent parallelism and reprogrammability, are fast becoming prevalent and easily fit on smaller boards such as PCI Mezzanine Cards (PMCs).
The PowerPC's AltiVec, 128-bit vector processor is the undisputed first choice for DSP where floating-point performance is the critical decision point. However, the new breed of FPGA is geared up to wipe out the AltiVec advantage for the great variety of the military's fixed-point DSP applications. Interestingly, although the AltiVec has been available for some time and appears in Freescale Semiconductor's recently announced dual-core MPC8641D embedded processor, there does not appear to be any interest within the industry in offering competitive (and hence better or faster) floating point solutions for military DSP applications.
FPGAs with their innate parallelism appear set to oust the traditional multiple-PowerPC solution from a broad range of DSP applications. FPGAs offer much reduced real estate, power consumption, and cost. Time-to-deployment pressure from end users is driving some COTS vendors to offer prepackaged FPGA-based hardware/software products for specific application segments.
Let’s talk numbers
The advent of the latest generation of FPGAs such as the Xilinx Virtex-4 or the Altera Stratix II — having as many as 100,000 logic cells, 400 DSP multiply/accumulate (MAC) elements and internal RAM, clocking at over 450 MHz — offers the potential to migrate and integrate DSP operations previously only performed by dedicated processors. The ability to process multiple data streams in parallel sets the FPGA solution apart from dedicated DSP or PowerPC alternatives.
Where ultimate performance is required on a single channel, the FPGA will always lose out — the AltiVec can perform a 64 x 64 MAC at single instructionrates (typically 1.5 GHz), whereas the FPGA will achieve 450 MHz for an 18 x 18 MAC — but the FPGA’s aggregate throughput from 400 MACs on multiple channels can far exceed that of a single PowerPC processor device in most applications. The DSP system designer can now choose from a number of design directions:
Front-end processing of multiple array sensors
Unlike a PowerPC or dedicated DSP processor, an FPGA offers many MAC elements to perform operations in parallel on incoming data streams. Previously this kind of parallelism required many PowerPCs to perform repetitive tasks such as filtering and decimation from each array of the sensor, with the attendant data distribution challenges. This data distribution is simple if all the PowerPCs are located on, for example, just a single VMEbus card, but much more complex if they are spread among many cards or even racks of cards where switched fabrics would be required. Using FPGAs can bring about big reductions at the critical front end, typically offering savings equivalent to one FPGA per 10x PowerPCs. Power, weight, space, complexity, and cost are conserved.
Complete System-On-a-Chip fixed-point DSP solutions
The FPGA provides a versatile set of external interface options such as LVDS, PCML, LVPECL, and HyperTransport with which to build multiple types of sensor interfaces. The DSP and logic elements can be used for filtering and FFT operations, plus onboard hard and soft processor cores and real-time operating systems are available for logical and system-level operations. Extensive toolkits and libraries are available for the development of FPGA architecture, routing, and software to suit the final application requirement.
With the notable exceptions of multiple-array radar and sonar applications, most military applications for DSP are relatively straightforward and can be closely coupled to the sensor itself. Typical of this class of application are:
- Video and image processing
- Communications (SDR)
- Weapons system sensors such as torpedoes, cruise missiles, ground-to-air missiles, air-to-air missiles, or surveillance UAVs.
Unlike the multiple-array radar and sonar applications that often use many hundreds of PowerPC-class processors plus a switched fabric for interconnection, these simpler applications listed above could be implemented by dedicated DSP devices (such as the TigerSHARC), ASICs, FPGAs, or by a much smaller number of PowerPC processors.
A potential application for a single FPGA device could be to form the basis of a typical rugged, man-portable SDR with multiple secure voice and data channels. Soft FPGA cores are available for filtering, IFFT/FFT (modulation and demodulation) using the FPGA's DSP elements, plus encryption and decryption — thus providing a number of communication channels in just one FPGA device. To offer complete, system-level functionality, this needs to be augmented with external interfaces to the RF components and the user, plus a general-purpose processor for operation of the user interface and regular diagnostics/prognostics of the completed system. Required user interfaces are:
- Serial RS-232/422 channels
- Discrete I/O
An ideal packaging solution for an FPGA front-end is the PMC module. Most generic SBCs from established military COTS vendors support the PMC concept of I/O, as indeed do many PowerPC-based DSP cards. The PMC module is independent of the SBC's processor type or bus architecture (for example VMEbus or CompactPCI), making it a versatile platform for many different applications. In this example, if the FPGA were implemented on a PMC-fomat module, it could then be mounted on a COTS 3U CompactPCI host SBC with either a Pentium or PowerPC processor. This combination of SBC and PMC would form the digital portion of the radio and would only occupy a single 0.8” slot width, 6.3” deep and 4” high.
Time-to-deployment of new FPGA designs
Time-to-deployment of new technology has become a critical factor in the military procurement process. Whereas projects would once take many years to reach combat status, with what was by then obsolete technology, timescales have shrunk. Introducing new capabilities such as security and surveillance now demands not just the latest technology but all the tools and application support required for their immediate use.
Though SOC FPGAs promise the benefits of technology leadership, there is considerable development effort required to reach deployment when undertaking new application designs. This is so even if it is based on a typical off-the-shelf solution such as a PMC module using the FPGA manufacturer's toolkits. Some COTS vendors have taken the idea further and developed prepackaged applications for their FPGA. PMC modules that include standard hardware interfaces and application-ready code can be used in areas such as SDR and video compression-based surveillance. Bundled COTS products reduce time-to-deployment to satisfy new expectations.
The TS-MPEG-4 bundled product from SBS Technologies shown in Figure 1 illustrates this product packaging strategy. It is based on a standard air- or conduction-cooled PMC module with an Altera Stratix EP1S30 FPGA, 128 MB of SDRAM, and a PCI interface to the host SBC. This PMC can be used in its basic form in many different applications with the customer developing code to suit. The external interfaces can be tailored by means of a unique micro-mezzanine mounted on the PMC module itself.
Figure 1: TS-MPEG-4 bundled product from SBS Technologies
In the module’s bundled form, the deliverable product includes all the code required for operation out of the box, plus physical interfaces to two RS-170 video sources and one RS-170 video output. Instead of using DSPs or general-purpose processors such as AltiVec-equipped PowerPCs, the supplied FPGA code compresses the two incoming video channels using MPEG-4, offering 15 to 20 percent better compression ratios than the widely used MPEG-2 standard. The card then streams compressed data over the PCI bus to the host SBC. On the host the MPEG-4 stream is encapsulated and passed to a network connection using UDP. Remote display clients supplied with the bundle can then decompress and display the decoded video streams. It should be noted that this is an FPGA-based system, reaping all the benefits of FPGAs that we’ve been describing.
Surveillance UAV example
Battlefield surveillance UAVs such as the Altair Predator B variant (Figure 2) are good examples of where packaged PMC-based FPGAs like the TS-MPEG-4 could be used for video capture and compression. This class of UAV usually flies at low to medium altitude over a battlefield or other area of particular interest and carries a number of video and, possibly, high-resolution single-shot cameras for a more detailed view of individual objects. The UAV will be controlled from a ground station that receives images from various cameras and are then displayed for analysis by the ground crew. The images may then also be relayed further up the command chain to build a complete tactical picture of the battlefield. The downlink from the UAV to the ground does not have the bandwidth to transmit all the video streams directly from the cameras in real time, driving the need for compression.
Figure 2: Altair Predator B variant
The mission computer for such a UAV is likely to be implemented using COTS VMEbus or CompactPCI modules. Because of the limited space, weight, and power budgets available in a UAV, 3U CompactPCI would again be an ideal format choice for the mission computer. FPGA-based PMC modules for video compression could be mounted on a host SBC or could occupy 3U slots using carrier cards. Video streams direct from the cameras in RS-170 format would be converted to MPEG-4 by the FPGAs, then encapsulated and downlinked by the mission computer for any of the ground-based operations required.
The FPGA with its unique and flexible architecture looks set to replace many of today's dedicated DSP solutions where its parallelism and aggregate throughput make possible big reductions in real estate and cost. Equally, the cost of time-to-deployment is becoming a critical factor for both the government and system integrator, and FPGA-based solutions often provide benefits as well. The availability of bundled, application-oriented COTS solutions, even though they may require minor customization for a particular end-use, promise to bring new FPGA-based DSP systems online faster and at lower cost.
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Duncan Young has worked in the defense industry for almost 40 years. Duncan was part of the management buyout team that formed Radstone Technology, and he initiated product development of the world’s first conduction-cooled VMEbus modules. He has also served on a number of standardization committees. Duncan is now an independent consultant and writes this column on behalf of SBS Technologies.
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