sFPDP: optimized data transport, an alternative to Ethernet

Story

May 10, 2021

The original VITA 17 standard, called Front Panel Data Port (FPDP), was defined to meet the need of high-speed and optimized communication between two points inside a processing cabinet, usually two VME racks.

The FPDP bus was intended to provide data transfer between two or more VMEbus boards as fast as 160 MB/sec with the lowest possible latency, while not compromising existing VMEbus and other connections on the chassis P1 and P2 connectors. FPDP was connected by means of an 80-conductor ribbon cable connector at the front panel of the VMEbus board. The wiring topology was in the form of a bus and multiple FPDP buses may coexist in a single VMEbus enclosure. FPDP was restricted to short distances (less than 1 m or 3.28 feet), mainly point-to-point and based on a very lightweight protocol focused on efficiency rather than functionality.

Beginning in the early 2000s, communication buses started moving from parallel to serial to offer higher bandwidth and longer distance capabilities. the VITA 17.1 serial FPDP (sFPDP) was created for the embedded industry. The initial instance, released in 2015, supported data rates as fast as 10 Gbaud.

As in the original parallel bus version, sFPDP is simple to implement and use. Engineers can implement it within an FPGA [field-programmable gate array] or ASIC [application-specific integrated circuit] with little difficulty.

sFPDP is a well-known protocol in defense, research, and medical markets. Major key players – Abaco Systems, Curtiss-Wright, Galleon EC, Mercury Systems, Pentek, and others – have designed many products to simplify the implementation of sFPDP that do not require additional FPGA development by the user. These products are used in embedded applications through rugged XMC modules or in lab equipment (data recorders or test benches). Thanks to widespread deployment, sFPDP is a staple for real-time applications in the field of sensor/computer links.

Thanks to these advantages, the sFPDP protocol has been widely adopted by the defense engineering community for applications in which high-speed links and real-time are mandatory. For example, it might be used for communication between complex sensors and processing units in harsh environments for applications in radar, sonar, test, and more.

The evolution of sFPDP

The sFPDP standard was updated in 2018 to move away from the concept of defined link rates and instead allowed any link rate to be used. The ANSI/VITA 17.3-2018 sFPDP Gen 3 standard also supports multilane channel bonding and advanced 64B/67B encoding to greatly increase the bandwidth capabilities of the link.

In addition, the serialization enabled the use of optical links, thereby significantly increasing distances of communication, boosting protection against electromagnetic interference, and opening the door for communication rates well above 10 Gb/sec.

Serial FPDP Gen 3.0 is conceptually based on the control signals and data structure used by Serial FPDP Gen 1.0, and consequentially, is designed to enable a straight­forward migration from sFPDP Gen 1.0 to sFPDP Gen 3.0. While not directly compatible with sFPDP Gen 1.0 at the physical level due to the different encoding scheme used, the protocol defined in this standard supports the same framing types, flow control, and link topologies as found in the sFPDP Gen 1.0 standard. The Physical Coding Sublayer (PCS) used by sFPDP Gen 3.0 is defined by the industry-standard Interlaken Framing Layer. Serial FPDP Gen 3.0 supports all of the features found in the Serial FPDP Gen 1.0 standard and also utilizes three different frame types (Serial Fiber Frames) to implement the four data frame types originally defined in the parallel FPDP standard. The primary objective of the Serial FPDP Gen 3.0 standard is to dramatically increase the bandwidth and scalability of the Gen 1.0 standard while remaining fully backward-compatible at the user interface level to ensure easy system upgrades from Gen 1.0 to Gen 3.0.

Serial FPDP Gen 3.0 offers many enhancements not found in the Gen 1.0 standard, namely multilane channel bonding, full CRC protection over all status and control signals, more than 99% bandwidth efficiency with 64B/67B encoding and scrambling, and use of individual user data block identification and error reporting that enables guaranteed delivery and retransmit mechanism.

The new standard allows a higher-than-10 Gb/sec transfer rate with no limit. In addition to this key feature, new functionalities expand the sFPDP field of applications: ANSI/VITA 17.3-2018 enables direct communication between sensors and processing boards but also enables communication with each other over greater distances.

The benefits of sFPDP

In opposition to “general-purpose” protocols or networks, the sFPDP protocol is dedicated to point-to-point communication. It reduces the protocol overhead and optimizes latency.

Thanks to sFPDP, the links are:

• Efficient: The ratio, total of transmitted data/effective volume of transmitted data, is close to 1
• Determinist: sFPDP’s ease of use enables FPGA implementation which free jitters from CPU and Linux
• Low-latency: The light and tunable data framing enables data transfers with low latency. This low latency is mandatory when talking about demanding applications like electronics countermeasures or simulation
• Reliable: Topologies offered by sFPDP protocol – point-to-point, copy, copy loop – prevent any loss of frames

At the same time, the industrial market has seen the emergence and popularization of 10 Gb Ethernet. In a few short years, this trend has spread into embedded applications. Today, system architects compare both protocols as equal. (Figure 1.)

Yet, sFPDP and 10 Gb Ethernet are not real competitors.

[Figure 1 | Typical serial FPDP process.]

sFPDP vs 10 Gb Ethernet: Let’s compare

Ethernet is ubiquitous, so hardware choices are limitless. An attractive advantage of Ethernet is the abundance of low-cost, high-performance equipment driven by the IT industry.

Ethernet has key advantages for embedded applications and real time:

1. Performance evolutions of Ethernet allow use in high-speed applications (10, 25, 40 Gb Ethernet)
2. Ethernet UPD implementation offers high-bandwidth capabilities for data transfer
3. Popularization and wide deployment of Ethernet leads to low-cost hardware dedicated to IT or consumer market

One more thing: Ethernet and its IP, TCP, or UDP protocols do not require special hardware or firmware design skills or specific hardware.

At first glance, sFPDP and Ethernet appear to be remarkably similar. Yet, if we look deeper, we will see differences in their concepts. These differences will impact the system performance of any project.

Data rate

Both support similar data rates at the physical layer. However, sFPDP is more efficient with its lighter protocol stack. This reduces software overhead and protocol layers making it a faster solution given equal hardware implementations. Winner: sFPDP.

Offload

One of the strengths of Ethernet UDP/IP is that it is “specific-hardware-free.” But it must be managed by the CPU and its operating system, which are not always the best tools to manage the protocol. Therefore, lot of CPU resources will be wasted and removed from application data processing. Alternatively, the user can implement a dedicated offload engine but that takes it all back to dedicated hardware. So: sFPDP can easily be implemented in an FPGA, frequently available in sensor applications, thus freeing the CPU from this task. Winner: sFPDP, if an FPGA is available.

Latency: sFPDP

sFPDP is a light protocol (no connection or session) which enables minimum latency, especially important in electronic countermeasures where real-time responses are critical. Even when throwing a lot of processing power at Ethernet, it will still come up short compared to sFPDP. Winner: sFPDP.

Determinism: sFPDP

Determinism is critical for real-time response. For example, time-stamping data frames for higher accuracy is important for recording analysis and accurate playback. This accuracy is impossible in the case where the CPU is used to execute a UDP/IP stack on Ethernet networks. To obtain equal accuracy, complex protocols must be deployed which are not compliant with embedded applications.

It’s possible to implement the UDP/IP protocol on FPGA, but it’s inefficient; choosing to run a heavy protocol with low determinism may not be wise if the platform is FPGA-based and sFPDP could be used.

Using an FPGA for sFPDP makes it possible to obtain a high degree of determinism for the reception and emission of data and to manage the protocol. Winner: sFPDP.

Topology

One of the biggest advantages of Ethernet is simplicity and flexibility. Thanks to the use of switches, hubs, or sniffers (for debug), complex, repetitive, and evolving networks can be built. However, the more complex the network, the less deterministic the data flow. Moreover, if the application implements point-to-point connection with Ethernet, most of the feature advantages of Ethernet are wasted.

sFPDP offers several fundamental topo­logy choices, whether basic system, flow control, bidirectional data flow, copy mode, and copy/loop mode that allow designers to – either temporarily or definitively – add communication nodes into a point-to-point link without modify the performance of the system. All of these modes support the maximum throughput performance. Winner: sFPDP.

The choice: Ethernet or sFPDP

At first sight, Ethernet appears to be a nice alternative for data transmission, driven by low-cost equipment; once the requirements of real-time applications are considered, though, the Ethernet option appears more challenging and riskier.

If the application requires data transmission with guaranteed high-performance data throughput, secured latency, and easy implementation, sFPDP is the way to go.

Products like the Techway RAVEN PCIe board with four VITA 17.3 sFPDP ports and FPGA processing can be the best way to connect to high-performance sen-
sors. Based on a Xilinx Kintex-7 FPGA, this sFPDP platform supports a data rate as fast as 10 Gb/sec per link. RAVEN includes support for flow control, CRC, framed/unframed, copy/loop modes; it’s also compliant with copper or fiber cabling. (Figure 2.)

[Figure 2 | The Raven is a VITA 17.3-compliant sFPDP PCIe platform with FPGA processing.]

 

Patrick Mechin, CEO of Techway, founded the company in 2003. Techway specializes in FPGA technology for real-time systems in defense and avionics applications. Patrick previously served as the Chief Operating Officer (COO) of VMETRO (Norway).

 

Philippe Marvin is a field application engineer at Techway; he originally joined Techway as a product manager. During the last 20 years, Philippe has worked for several companies specializing in the embedded defense market, including VMETRO (Norway), Curtiss-Wright (U.S.), and Gaci (France).

Techway • https://www.techway.fr/