Articles 1 - 4
Radar/EW
Signal processing FPGAs with hard floating-point - No compromise - Story
June 02, 2015
Since the dissolution of cutting-edge digital signal processor (DSP) product lines designers have been forced to develop using either FPGAs integrated with time-consuming fixed-point DSP blocks, or floating-point general-purpose graphics processing units (GPGPUs) that leave performance on the table in high-end signal processing systems. But now, with the release of Altera’s Generation 10 FPGAs that integrate hardened IEEE 754-compliant floating-point operators, why compromise?
Radar/EW
Radar/EW
Digital channelizer implemented on COTS FPGA board: A flexible solution for military signal processing - Story
January 29, 2014
One of the major challenges of modern military Digital Signal Processing (DSP) is dealing with the ever-widening bandwidth of digitized signals. Until fairly recently, analog-to-digital converters (A/D converters) were limited to only hundreds of MHz, so anything beyond that had to be dealt with using traditional RF/analog methodologies. Now that A/D converters are available in the GHz range, much wider band processing is moving to the digital domain.
Radar/EW
Floating-point coprocessors enable FPGAs to replace DSPs - Story
June 01, 2012
A coprocessor can greatly improve the productivity and algorithmic flexibility of an FPGA, thereby enabling it to handle a larger part of a signal processing implementation.
Articles 1 - 4
