Sealevel Systems, Inc.
2779 Greenville Highway
Liberty, SC 29657 https://www.sealevel.com/?gclid=Cj0KCQjwybD0BRDyARIsACyS8mvDWLwzNOu--B8B7IMD0ATPEzf0pFF3qPlNJx1NlR8DaMRYHXufHr4aAnhPEALw_wcB
Liberty, SC 29657 https://www.sealevel.com/?gclid=Cj0KCQjwybD0BRDyARIsACyS8mvDWLwzNOu--B8B7IMD0ATPEzf0pFF3qPlNJx1NlR8DaMRYHXufHr4aAnhPEALw_wcB
Articles related to Sealevel Systems, Inc.
Avionics
PMC card for avionics interfaces with configurable channels - Product
February 14, 2018
Sealevel?s PMC HyperBoard is a multi-standard PCI mezzanine card (PMC) that is compatible with MIL-STD-1553B and MIL-STD-1760 networking and interface standards. As well, each channel can be configured independently to work with H009 and WB-194 interfaces in conjunction with MIL-STD-...
Avionics
Renewed partnership enables MIL-STD-1553 product offerings at AFCEA WEST 2018 - News
February 08, 2018
SAN DIEGO. Sital Technology and Sealevel Systems Inc. officials renewed their partnership, in which Sealevel representatives will service the United States territory for Sital [headquartered in Israel]. Officials are showcasing the new product offerings that stem from the partnership at AFCEA WEST 2018.
Unmanned
Comms
Flat-panel rugged touchscreen computer intended for harsh, hazardous environments - Product
November 16, 2014
The SeaPAC R9-8.4 from Sealevel Systems combines a RISC-based embedded computer with a bright LED-backlit thin-film-transistor LCD touchscreen to create a ruggedized, flat-panel computer intended for use in a variety of human-machine interface applications.
Avionics
Comms
Avionics
MIL-STD-1553 IP cores challenge traditional IC implementation - Story
March 11, 2014
Forty years since its release, MIL-STD-1553 is evolving from traditional Integrated Circuits (ICs) to Intellectual Property (IP) cores integrated with Field Programmable Gate Arrays (FPGAs). The advantages of IP core implementation include cost reduction, the ability to upgrade and adapt a design over time, a smaller size footprint, and improved sourcing. Designers choosing IP cores must consider validation testing, code size, FPGA support, and compatibility with legacy software.
