Military Embedded Systems

Designing OpenVPX systems to support Gen3 >10 Gbaud signaling


September 30, 2013

Bob Sullivan


Signal Integrity (SI) is becoming an increasingly critical consideration for designers of OpenVPX systems. While system integrators first confronted some SI issues as the embedded industry made the performance advance from Gen1 at 3.125 Gbaud to Gen2 at 6.25 Gbaud signaling, the current transition to Gen3 >10 Gbaud signaling rates, nearly doubling the bandwidth of Gen2 OpenVPX, requires a significant increase in the level of tools, capability, expertise, and know-how to ensure successful design and implementation of a robust latest generation, OpenVPX system.

The MultiGig VPX connector was originally designed for 6.25 Gbaud signaling rates. With Gen3 OpenVPX signaling increasing to >10 Gbaud signaling rates, we are pushing the MultiGig connector to its physical limits. Unless system designers familiarize themselves with the greater importance that SI plays when implementing these new faster signaling rates, they put the success of their new Gen3 OpenVPX designs at risk.

Simulation studies for Gen3 >10 Gbaud signaling

To augment current research on Gen3 OpenVPX SI, extensive simulation studies were undertaken by a highly regarded third-party signal integrity expert -- Teraspeed Consulting Group. The simulations were designed to analyze the MultiGig connector’s physical limits and to perform complete end-to-end modeling over various backplane lengths and to ensure robust performance at the system level.

Testing the limits of the VPX Connector

The physical limits of the MultiGig connector in regard to operation at higher OpenVPX signaling rates has been recognized and understood for some time. There are in fact several well-known SI impairments that can result from the internal design of the VPX connector. These impairments, combined with issues related to the physical geometry of the VPX connector’s footprint, must be aggressively managed in order to ensure reliable Gen3 10 Gbaud operation. These connector-related impairments include:

• Return Loss (RL) due to impedance discontinuities in the VPX connector footprints;
• crosstalk due to the physical geometry of the VPX connector footprints;
• exaggeration of the already high crosstalk, due to common mode signals (mode conversion) resulting from weave skew in the differential pairs; and
• resonances in the vias and connector that degrade Insertion Loss (IL), RL and crosstalk in the critical 5 GHz Nyquist region at 10 Gbaud

Simulation testing results

The simulation testing showed that RL and crosstalk peaking in MultiGig connector vias occurs in the 4 to 5 GHz band, near Nyquist, while Insertion Loss also degrades (see the dip in insertion loss in Figure 1). This squeezes signal-to-noise ratio in the critical Nyquist region. Figure 1 below illustrates this phenomenon.

Figure 2 (left image) shows the 40 Gigabit Ethernet (GbE) Eye Diagram that results from the worst-case permutation. While the use of good high-speed design rules would normally be sufficient to achieve reliable 10 Gbaud operation, these results show that approach to be insufficient with the VPX connector.

As a result of the simulation and modeling effort, Curtiss-Wright developed a new set of high-speed design rules. Figure 2 (right image) shows the 40 GbE eye diagram that results from the worst-case permutation, using the newly developed design rules. This shows that by avoiding the worst-case permutations it’s possible to achieve a robust channel supporting >10 Gbaud signaling.

Research shows that achieving a robust OpenVPX solution at Gen3 signaling rates of >10 Gbaud is a daunting task. During our research, more than 11,000 simulation cases were run. The results of this research showed that a significant percentage of the permutations of these parameters, further exacerbated by manufacturing tolerance variations, produced channels that do not work reliably at 10 Gbaud. (See Figure 3).

While, one might assume that selecting low loss laminate materials would serve to mitigate these failures, it turns out that the problem is highly complex, and cannot be solved with that approach. Aggressive design rules need to be applied to both the modules and the backplane to avoid the problem permutations.

SI Modeling Results

The results of the SI modeling provide very useful data that helps define best-practice rules for designing OpenVPX systems with Gen 3 signaling rates. To mitigate the SI impairment issues associated with the VPX connector requires the optimization of several design parameters:

• module and backplane trace length optimization;
• module and backplane materials selection;
• module and backplane weave skew mitigation;
• module and backplane stack-up optimization;
• module and backplane via tuning;
• controlling module and backplane manufacturing tolerance variations;
• module AC capacitor circuit optimization; and
• module device package breakout optimization.

While the simulation and modeling show that it is possible to achieve robust Gen3 >10 Gbaud signaling in OpenVPX systems, it also makes clear that successful designs require a high degree of care and know-how. The design of both modules and backplanes must be optimized in order to achieve robust Gen3 >10 Gbaud signaling. For more information, visit


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