Military Embedded Systems

OpenVPX enables tightly coupled FPGA and CPU processing for unmanned EW platforms


July 31, 2013

Eran Strod


OpenVPX brings together high-speed parallel processing FPGAs with the software capability of CPUs to meet the most challenging sensor processing applications for unmanned platforms.

Today’s UAVs, UGVs, and UUVs are being enhanced with an increasing amount of sensors. The huge amount of incoming data from these Electronic Warfare (EW) sensors needs to be processed as close to real-time as possible. As processing elements go, the FPGA is ideal as a sensor interface. It is great at performing a fixed algorithm on parallel data with unmatched speed and very low latency. High-end FPGAs are equipped with a large number of serial or parallel interfaces, allowing them to input large quantities of raw data that is then preprocessed.

However, the modern sensor does not exist in isolation. It lives in the context of a “system of systems” with interconnectedness to computers, tablets, and handheld devices. The software protocols that connect smart devices together over a large network run on CPUs, not FPGAs. For example, it is relatively straightforward to run an Ethernet MAC in an FPGA. One can even run TCP/IP although it is a little cumbersome. It is harder yet to run higher-level functions: for example, sockets, FTP, http, data movement middleware like MPI, or a publish/subscribe middleware like DDS. The FPGA without these enabling software components is isolated. It can collect data, and it can process that data, but it cannot easily share the data with the outside world. The unmanned platform’s data must be shared to be actionable.

The connectivity functions on an unmanned platform’s sensor processing system belong on a CPU that has easy access to software components, stacks, and applications. There are literally billions of lines of open source software, most of which is written for the x86 architecture. Software infrastructure running on CPUs provides the framework and the protocols for applications to connect the sensor to systems and users. The best way to interface an FPGA and CPU in an open architecture is to use OpenVPX (VITA 65) because it was built from the ground up to provide a mechanical and electrical framework for heterogeneous computing benefitting unmanned platforms’ data processing.

Wideband EW for unmanned platforms

The ideal sensor processing architecture optimized for an EW unmanned platform has a very high-speed receive function and a high-speed transmit function connected to a common FPGA. The fastest COTS ADCs on the market today contain technology that is brought to the mil/aero market from the test equipment market. Data centers, communications equipment vendors, and OEMs are on the verge of migrating to 10 Gbaud signaling in nearly every domain of computing. Test equipment vendors such as Tektronix are meeting this need with very high-speed probe technology, which at its base contains an ADC converter. The technology that is used to probe 40 GbE, InfiniBand FDR, or PCI Express 3.0 is based upon very high-speed ADCs. While there are very advanced technologies in the works, ADC technology able to acquire 12 GSps at 8 bits of resolution is now crossing the chasm and fast becoming a volume market.

This is a very powerful sampling capability when it is applied in the mil/aero unmanned platforms setting for wideband data acquisition. 12 GSps at 8 bits amounts to 12 GBps of raw data, an enormous processing and data movement challenge. The processing power needed to find signals of interest in this relentless stream of raw bits is tremendous. The latest FPGAs, such as the Virtex-7 from Xilinx, combine the processing resources required to meet this processing challenge with the high-speed signaling required to ingest tremendous amount of data. The FPGA is able to keep up with a 12 GBps input data stream, process it in real time, and yet still has enough high-speed signals to generate a waveform response. Turning to state-of-the-art DAC technology, from test equipment vendor Tektronix, one finds a 12 GSps 10-bit DAC now achieving the technical maturity required for deployment in unmanned systems.

The collocation of the ADC and DAC within the same physical FPGA device brings the latency of response to the lowest possible level. This set of emerging technologies is now able to increase wideband EW performance 2-4 times over what has been previously possible with open architecture COTS components. The 12 GSps at 8 bits ADC and 12 GSps 10-bit DAC can be achieved in COTS form by a 6U OpenVPX FPGA-based computing module. The FPGA node can support data plane interfaces using Direct Memory Access (DMA), but it has a difficult time running the specific high-level protocols and middleware that enable it to reach across the system fabric or wide-area network. This makes it difficult for an FPGA to provide the wide area connectivity that unmanned sensors require to supply data to analysts and ground forces. CPUs offer the flexibility needed for this aspect of the EW system. The FPGA and CPU blocks must be connected by a high-speed OpenVPX backplane interface to avoid bottlenecks.

CPUs provide flexibility, connectivity

As mentioned earlier, a CPU is best at running the middleware that connects the sensor in the UAV, UGV, or UUV to the outside world. The leading choice in this category is the Intel 4th generation Core i7 CPUs (formerly named “Haswell”). This brand new Core i7 processor for mobile computing is based on a low-power embedded implementation of Intel’s 22 nm microarchitecture, and is ideal for sensor computing. The CPUs contain integrated 16-lane PCIe Gen 3 interfaces, allowing 16 GBps data movement between the FPGA and CPU memory. The resulting data rate is effectively more than the speed of the entire ADC, which serves to provide a great deal of flexibility to applications that interface to the outside world. The CPU runs an operating system, typically Linux or VxWorks, and executes a stack that interfaces to the data plane. Figure 1 shows how the FPGA and CPU are connected via this high-speed pipe.


Figure 1: A 6U OpenVPX FPGA-based computing module and an OpenVPX multiprocessing DSP module bring FPGA and CPU processing together.

(Click graphic to zoom by 1.9x)




The data plane in an embedded system is typically one of three types of fabrics: 10/40 GbE, InfiniBand, or RapidIO. The data plane fabric is used to transfer data between processing elements in the system. In the case of InfiniBand or RapidIO, there usually must be a bridge to Ethernet before data can be transmitted to the outside world.

One of the most powerful capabilities provided by a CPU is the ability to execute publish/subscribe middleware such as Data Distribution Service (DDS). Pub/sub is a message-oriented middleware that allows data sources to publish to interested parties called subscribers. The subscribers are able to tune in specifically to the data that they want and are able to set quality-of-service parameters that are specific to their needs. For example, a high-speed device may request a continuous stream of images. A slower device may request one image at a time. Some devices may only want to see an image once and might wish that it be discarded after being viewed. Others may wish to see the oldest images (FIFO or First-In-First-Out), instead of the most recent (LIFO or Last-In-First-Out). The publish/subscribe middleware allows data publishers and subscribers to share a virtual link without having to manage and be aware of the service requirements of each other and various other system publishers and subscribers.

Another powerful middleware is the Message Passing Interface (MPI). MPI is a portable, language-independent protocol used to share data among distributed processors such as CPUs. It has become a de facto standard for communication among high-performance compute clusters and is used by many of the TOP500, the most powerful computers in the world. Middleware like MPI is an essential element in the effective scaling up of a CPU cluster to a large High Performance Embedded Computing (HPEC) system.

In addition to the ability to run sophisticated middleware, CPUs make it easy to add features that are common in PCs such as:

  • Display – CPUs support high-resolution image rendering interfaces like embedded DisplayPort (eDP). DisplayPort is a digital communication interface that utilizes differential signaling to achieve a high-bandwidth bus interface designed to support connections between PCs and monitors, projectors, and TV displays. DisplayPort is the first display interface to rely on packetized data transmission.
  • Storage – Serial ATA (SATA) is an interface that connects to mass storage devices such as hard disk drives and optical drives. Sensor processors on unmanned airborne platforms, land vehicles, or naval vessels are often connected to the enterprise network on a wireless or satellite link.
  • Peripherals – These are connected via the ubiquitous Universal Serial Bus (USB), which connects to many electronic devices including keyboards, pointing devices, and other adapters.


Figure 2: The Curtiss-Wright dual Intel Core i7 4700EQ-based CHAMP-AV9 board

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OpenVPX conquers heterogenous processing

OpenVPX is an ideal platform for heterogeneous systems that perform the processing required for high-speed radar, image processing, SIGINT, and EW in unmanned vehicles. An example is Curtiss-Wright’s OpenVPX-based, dual Intel Core i7-4700EQ CHAMP-AV9 DSP module (Figure 2) – including 32 lanes of PCIe 3.0 expansion plane and 16 lanes of 10 Gbaud data plane signaling on the OpenVPX backplane. The module utilizes OpenVPX to bring together the high-speed parallel processing of FPGAs with the software capability of CPUs. The result of such a paradigm: Designers are able to conquer the most challenging sensor processing application requirements for unmanned platforms.

Eran Strod is System Architect at Curtiss-Wright Controls Defense Solutions. He can be contacted at [email protected].

Curtiss-Wright Controls Defense Solutions 613-254-5112


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