Military Embedded Systems

I/O mezzanines for FPGA-based reconfigurable computing


August 11, 2010

Steve Edwards


Is PMC, XMC, or FMC best for reconfigurable FPGA-based computing? The answer hinges upon design issues. However, depending on application requirements, it is probable that rugged FPGA I/O will be served by the PMC, XMC, or FMC open standards.

Which mezzanine format – the PCI Mezzanine Card (PMC), Switched Mezzanine Card (XMC), or FPGA Mezzanine Card (FMC) – is best for reconfigurable FPGA-based computing applications? The answer depends on design issues such as application details, perception of risk, development timeline, and personal preference. FPGAs are ideal for high-bandwidth I/O applications because they connect directly to I/O devices to ensure low latency and support high-speed front-end DSP.

Any of these three mezzanine approaches should be compared with monolithic board technology, for example, a single Printing Wiring Board (PWB) with all FPGA functionality onboard. While representing the least flexible and possibly most costly approach, the monolithic card usually provides the best technical option because it does not have the restrictions imposed by segmenting the design, such as the number of connector I/O pins to the mezzanine. However, depending on application requirements, it is probable that rugged FPGA I/O will be served by the PMC, XMC, or FMC open standards.

PMC and XMC with FPGAs?

PCI-X (PMC) or PCI Express (XMC) latency is typically in the order of 1 to 2 microseconds and delivers bandwidths of just a few GBps, which is sufficient for some of the more demanding applications, but not for all. For some FPGA applications, PCI, PCI-X, PCI Express, and Serial RapidIO can actually dilute the advantages of using FPGAs, which excel with parallel streaming dataflows. The FMC module, similar in height and width to a PMC but approximately half the length, is designed to carry only the I/O devices and connect them directly to the FPGA device on the host board. This approach enables interface optimization among the I/Os, and the FPGA and also delivers a reduction in real estate, cost, latency, and power while boosting bandwidth.

FPGAs are ideal for high-bandwidth, high-resolution I/O because of the many I/O connections provided. This is especially true if high-speed memory is required to buffer the input or output data streams. These applications usually demand the largest FPGA packages with the most available I/O pins. Because these devices tend to be large, measuring 35 x 35 mm or more, they can violate the PMC or XMC specifications’ “no go” area across the module’s middle where components are banned. This restricted area forms part of the card’s primary thermal interface for conduction-cooled cards and serves as a mechanical fixing area to marry with stiffening bars on the host. The result: Using large FPGA packages on PMC or XMC cards can encroach on the real estate where the designer would ideally want I/O devices placed.

Relative sizes of PMC/XMC and FMC modules

The FMC has a simplified power requirement that frees up valuable module real estate for additional I/O. FMC measures only about a half the PWB area of a PMC or XMC, but an FMC can often provide greater I/O functionality compared to PMCs and XMCs because of the PMC and XMC “no go” restriction mentioned earlier. The useful space for I/O devices on PMC/XMC can sometimes end up only a quarter of the overall real estate of the XMC. Figure 1 shows the relative sizes of PMC, XMC, and FMC modules.


Figure 1: The relative sizes of PMC, XMC, and FMC modules

(Click graphic to zoom by 1.6x)




Rugged PMC and XMC versus FMC cooling

FMCs also simplify cooling challenges, especially on small form factor cards. When plugged onto a 3U host card such as 3U VPX, a PMC or XMC covers the majority of the host’s real estate. Any hot devices on the host will be located beneath the XMC, seriously affecting cooling. Furthermore, an XMC mezzanine’s devices are located facing the host, which places the heat generating devices opposite those on the host and increases the cooling problem. In 6U designs, the situation is not much better. While some of the 6U host’s real estate is not covered by the mezzanine card(s), the thermal paths to either the cooling air inlet or cold wall interface are longer.

Because of FMC’s smaller size, less of the host board is covered by the mezzanine. Appropriate FMC host design allows for suitable heat sinks to be implemented in the areas not restricted by mezzanine placement. And since only the I/O devices, not the FPGA, are on the module, the FMC is easier to cool. The FMC specification limits the power dissipation of a single-width module to 10 W.

FMC complements PMC and XMC

While FMCs were designed for front-panel I/O, Curtiss-Wright Controls Embedded Computing (CWCEC) addresses this limitation with right-angle connectors and a specially designed strain-relief bracket to secure the connectors and minimize vibration damage to delicate connectors. This has been implemented on the 3U FPE320 board and is designed into or planned for all of the company’s future FMC-based products.

FMC does not compete with PMC or XMC, but rather complements it, specifically for high-bandwidth, low-latency applications. Depending on the application, it is likely that rugged FPGA I/O will be serviced by one of these open standards. Where they cannot meet the requirements, the monolithic approach provides the safety net. Determining which approach works best will depend on application specifics.

To learn more, e-mail Steve at [email protected].


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