An innovative approach to communication processors: Multicore Done RightOther
November 13, 2009
Asymmetric multicore architectures are needed to achieve wire-speed, deterministic performance at the lowest power and cost.
Generic multicore processors have been promoted as the solution to networking communication processing. In reality, they can’t address the scalability, determinism, and ease of programming required for next-generation networking infrastructure. An asymmetric multicore approach that blends multicore processors with networking-optimized accelerator engines and C-programmable libraries meets the challenges of next-generation networks.
Achieving deterministic performance is a key requirement for network operators to ensure reliability across wide variations of traffic profiles and applications. Multicore processors can meet performance challenges when running an application on a single, dual-core, or quad-core processor. However, when scaling to eight cores or beyond, performance scaling usually degrades. There are cases where eight cores deliver no better performance than four, and 16 cores actually run slower than eight.
Networking applications tend to be data-intensive, and generic multicore processors are highly susceptible to the impacts of memory latency on performance. The nonlinearities of memory latency (Figure 1) with regard to memory load combined with the nonlinearities of processor performance relative to memory latency can lead to unpredictable and unreliable performance. The innovative approach taken by LSI to solving this problem is asymmetrical multicore processors, which combine general-purpose processors with specialized accelerators for particular data-intensive tasks, resulting in an optimal, scalable solution.
Figure 1: Asymmetrical multicore processors improve performance predictability by combining general-purpose processors and accelerators to address the nonlinearities of memory latency.
(Click graphic to zoom by 1.9x)
Networking infrastructure applications tend to involve complex processing, intense memory utilization, and real-time, deterministic requirements. Asymmetric architectures address these challenges by seamlessly allocating the work between general-purpose multicore processors and specialized acceleration engines. These accelerators are specifically designed to tolerate memory latencies and perform predictably. This approach also enables the application to be built using fewer general-purpose multicore processors with far fewer lines of code. The asymmetric approach simplifies scaling challenges and delivers more deterministic performance at lower cost and power.
Networking applications demand a flexible approach to OSs. This flexibility is required not only to meet application requirements, but also to support the smooth migration of OEM legacy software and give designers the ability to choose the right OS for a particular application. It is important to simultaneously support multiple OSs on different cores without introducing overhead. At LSI, our hardware and software has been architected from the ground up with all this in mind, providing flexible support for the range of OSs used in networking applications.
Software tools such as compilers, simulators, and debuggers are required to support these processors. Simulators must be fast, support real-world throughput and traffic types, and perform accurately for software debugging. Ideally, tools are integrated to enable end-to-end software development in a single environment.
LSI has developed an integrated software development environment through six generations of communications processors. These tools have been hardened through many years of real-world deployment. LSI provides an Advanced Development Kit (ADK) consisting of highly scalable, customer-extensible modules that can be combined to enable quick and easy application development. These function-specific modules seamlessly enable rapid development of applications leveraging the asymmetric multicore architecture for wireless, wireline, and enterprise networking.
The ever-increasing performance demands of next-generation networks and applications, coupled with user expectations of reliability and quality of service, require purpose-built asymmetric multicore architectures to achieve wire-speed, deterministic performance at the lowest power and cost. LSI solutions for networking infrastructure applications are optimized with the right combination of multicore processors and accelerators to deliver scalable, reliable, and deterministic performance. We call this “Multicore Done Right.”
Jeff Richardson is responsible for LSI silicon solutions across all segments of data networking and storage. Jeff has held executive positions at Intel and engineering positions at Altera, Chips and Technologies, and Amdahl. He has a BS in Electrical Engineering from the University of Colorado.