Military Embedded Systems

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Interface Concept

3 Rue F?lix Le Dantec
Quimper, Brittany 29000
[email protected]
Interface Concept
Articles related to Interface Concept

FEATURED VIDEO: SOSA Technical Standard key contributors team to demonstrate a platform to demo alignment and goals - Video

May 04, 2021

SOSA CONSORTIUM. A group of key contributors to the emerging SOSA Technical Standard teamed up to put together a platform that demonstrates the value of the alignment and interoperability goals driving the SOSA Consortium mission.


SOSA-aligned 3U VPX Ethernet switch designed for low-SWaP systems - News

February 11, 2021

FRANCE. Interface Concept, company specializing in the design and manufacturing of COTS embedded boards and systems, announced the ComEth4412a, a 3U VPX dual plane hybrid PCIe Gen 3 and 40 Gigabit Ethernet Switch, designed in alignment with the Sensor Open Systems Architecture (SOSA) technical standard.


Thales selects Interface Concept's ComEth4510a for radar application - News

March 22, 2018
QUIMPER, France. Thales engineers have integrated Interface Concept's ComEth4510a, a 6U OpenVPX Gigabit & 10/40 Gigabit L3+ Ethernet switch and IP Router in a radar application.

Increasing data-transfer performance in VPX systems - Story

November 16, 2017
The combination of digital simulation and high-performance calculation is radically transforming industry and research. It is now possible to develop products and services without spending precious time and dollars on replicating work already done. This is certainly the case in the military and aeronautics fields, particularly in the area of building size, weight, and power (SWaP)-constrained embedded computing architectures for use in electronic warfare and radar applications.

FPGA coprocessors for low-power adaptive beamforming in hybrid VPX HPEC systems - Story

February 10, 2017
Beamforming techniques have become very important in the fields of radar, electronic warfare (EW), sonar, wireless communication, and medical imaging. These enable continuous formation of beams from array antennas (or array transducers) towards a tracked target - or a moving user in the case of wireless communication - and cancellation of all the interfering signals coming from other angles. For tactical or airborne radar and EW solutions, the execution speed of the beamforming algorithms and the low power consumption are critical. In these situations, VPX high-performance embedded computing (HPEC) hybrid field-programmable gate array (FPGA) and CPU systems appear to be the best suited approach.

FPGA coprocessors for acceleration of shape recognition algorithms in hybrid VPX HPEC systems - Story

November 15, 2016
To reach the level of performance requested by the latest military specifications, electronic warfare (EW) systems designers rely more and more on VPX high-performance embedded computing (HPEC) platforms. To handle the global IP traffic growth - predicted to reach 132 exabytes (EB) per month in 2018, according to Cisco's Visual Network Index - electronic systems must manage the data flow in and out of the semiconductor devices. Designers of field-programmable gate arrays (FPGAs) have developed devices offering high bandwidth and performance with very high-speed interfaces that can bring superior parallel processing power. This reality enables the design of high-performance hybrid HPEC systems that can be used for such demanding applications as ultrafast shape-recognition systems.